Lines Matching +full:0 +full:x3000
18 #size-cells = <0>;
49 CPU0: cpu@0 {
52 reg = <0x0 0x0>;
60 reg = <0x0 0x100>;
68 reg = <0x0 0x200>;
76 reg = <0x0 0x300>;
84 reg = <0x0 0x400>;
92 reg = <0x0 0x500>;
100 reg = <0x0 0x600>;
108 reg = <0x0 0x700>;
122 arm,psci-suspend-param = <0x00010000>;
165 reg = <0x0 0x12000000 0 0x20000>, /* GICD */
166 <0x0 0x12040000 0 0x100000>; /* GICR */
171 redistributor-stride = <0x0 0x20000>; /* 128KB stride */
180 reg = <0 0x20100000 0 0x4000>;
183 ranges = <0 0 0x20100000 0x4000>;
185 apahb_gate: clock-controller@0 {
187 reg = <0x0 0x3000>;
197 reg = <0 0x31050000 0 0x9000>;
203 reg = <0 0x322a0000 0 0x8000>;
209 reg = <0 0x32310000 0 0x1000>;
215 reg = <0 0x32320000 0 0x1000>;
221 reg = <0 0x32330000 0 0x1000>;
227 reg = <0 0x32340000 0 0x1000>;
233 reg = <0 0x32350000 0 0x1000>;
239 reg = <0 0x32360000 0 0x1000>;
245 reg = <0 0x32390000 0 0x3000>;
248 ranges = <0 0 0x32390000 0x3000>;
250 dpll0: clock-controller@0 {
252 reg = <0x0 0x100>;
260 reg = <0 0x323b0000 0 0x3000>;
263 ranges = <0 0 0x323b0000 0x3000>;
265 mpll1: clock-controller@0 {
267 reg = <0x0 0x100>;
275 reg = <0 0x323c0000 0 0x3000>;
278 ranges = <0 0 0x323c0000 0x3000>;
280 pll1: clock-controller@0 {
282 reg = <0x0 0x3000>;
292 reg = <0 0x323e0000 0 0x3000>;
295 ranges = <0 0 0x323e0000 0x3000>;
297 pll2: clock-controller@0 {
299 reg = <0x0 0x100>;
309 reg = <0 0x323f0000 0 0x3000>;
315 reg = <0 0x327d0000 0 0x3000>;
318 ranges = <0 0 0x327d0000 0x3000>;
320 aonapb_gate: clock-controller@0 {
322 reg = <0x0 0x3000>;
332 reg = <0 0x327e0000 0 0x3000>;
335 ranges = <0 0 0x327e0000 0x3000>;
337 pmu_gate: clock-controller@0 {
339 reg = <0x0 0x3000>;
349 reg = <0 0x3350d000 0 0x1000>;
352 ranges = <0 0 0x3350d000 0x1000>;
354 audcpapb_gate: clock-controller@0 {
356 reg = <0x0 0x300>;
364 reg = <0 0x335e0000 0 0x1000>;
367 ranges = <0 0 0x335e0000 0x1000>;
369 audcpahb_gate: clock-controller@0 {
371 reg = <0x0 0x300>;
379 reg = <0 0x60100000 0 0x3000>;
382 ranges = <0 0 0x60100000 0x3000>;
384 gpu_clk: clock-controller@0 {
388 reg = <0x0 0x100>;
396 reg = <0 0x60110000 0 0x3000>;
402 reg = <0 0x62200000 0 0x3000>;
405 ranges = <0 0 0x62200000 0x3000>;
407 mm_gate: clock-controller@0 {
409 reg = <0x0 0x3000>;
417 reg = <0 0x71000000 0 0x3000>;
420 ranges = <0 0 0x71000000 0x3000>;
422 apapb_gate: clock-controller@0 {
424 reg = <0x0 0x3000>;
431 reg = <0 0x20200000 0 0x1000>;
439 reg = <0 0x32080000 0 0x1000>;
449 reg = <0 0x62100000 0 0x1000>;
458 reg = <0 0x3c002000 0 0x1000>;
472 #size-cells = <0>;
487 reg = <0 0x3c003000 0 0x1000>;
504 reg = <0 0x3e001000 0 0x1000>;
519 #size-cells = <0>;
521 port@0 {
522 reg = <0>;
554 reg = <0 0x3e002000 0 0x1000>;
580 reg = <0 0x3e003000 0 0x1000>;
606 reg = <0 0x3e004000 0 0x1000>;
621 #size-cells = <0>;
623 port@0 {
624 reg = <0>;
642 reg = <0 0x3e005000 0 0x1000>;
656 #size-cells = <0>;
658 port@0 {
659 reg = <0>;
690 reg = <0 0x3f040000 0 0x1000>;
707 reg = <0 0x3f140000 0 0x1000>;
724 reg = <0 0x3f240000 0 0x1000>;
741 reg = <0 0x3f340000 0 0x1000>;
758 reg = <0 0x3f440000 0 0x1000>;
775 reg = <0 0x3f540000 0 0x1000>;
792 reg = <0 0x3f640000 0 0x1000>;
809 reg = <0 0x3f740000 0 0x1000>;
828 ranges = <0 0x0 0x70000000 0x10000000>;
830 uart0: serial@0 {
833 reg = <0x0 0x100>;
842 reg = <0x100000 0x100>;
850 reg = <0x1100000 0x1000>;
862 reg = <0x1400000 0x1000>;
877 ranges = <0 0x0 0x32000000 0x1000000>;
881 reg = <0x100000 0x100000>;
883 #size-cells = <0>;
884 sprd,hw-channels = <2 0x18cc>, <3 0x18cc>, <13 0x1854>, <15 0x1874>,
885 <17 0x1844>,<19 0x1844>, <21 0x1864>, <30 0x1820>,
886 <35 0x19b8>, <39 0x19ac>;
893 #clock-cells = <0>;
900 #clock-cells = <0>;
907 #clock-cells = <0>;
914 #clock-cells = <0>;