Lines Matching +full:non +full:- +full:coresight
1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <dt-bindings/clock/sprd,sc9863a-clk.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #address-cells = <2>;
15 #size-cells = <0>;
17 cpu-map {
48 compatible = "arm,cortex-a55";
50 enable-method = "psci";
51 cpu-idle-states = <&CORE_PD>;
56 compatible = "arm,cortex-a55";
58 enable-method = "psci";
59 cpu-idle-states = <&CORE_PD>;
64 compatible = "arm,cortex-a55";
66 enable-method = "psci";
67 cpu-idle-states = <&CORE_PD>;
72 compatible = "arm,cortex-a55";
74 enable-method = "psci";
75 cpu-idle-states = <&CORE_PD>;
80 compatible = "arm,cortex-a55";
82 enable-method = "psci";
83 cpu-idle-states = <&CORE_PD>;
88 compatible = "arm,cortex-a55";
90 enable-method = "psci";
91 cpu-idle-states = <&CORE_PD>;
96 compatible = "arm,cortex-a55";
98 enable-method = "psci";
99 cpu-idle-states = <&CORE_PD>;
104 compatible = "arm,cortex-a55";
106 enable-method = "psci";
107 cpu-idle-states = <&CORE_PD>;
111 idle-states {
112 entry-method = "psci";
113 CORE_PD: core-pd {
114 compatible = "arm,idle-state";
115 entry-latency-us = <4000>;
116 exit-latency-us = <4000>;
117 min-residency-us = <10000>;
118 local-timer-stop;
119 arm,psci-suspend-param = <0x00010000>;
124 compatible = "arm,psci-0.2";
129 compatible = "arm,armv8-timer";
131 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, /* Physical Non-Secure PPI */
137 compatible = "arm,cortex-a55-pmu";
149 gic: interrupt-controller@14000000 {
150 compatible = "arm,gic-v3";
151 #interrupt-cells = <3>;
152 #address-cells = <2>;
153 #size-cells = <2>;
155 redistributor-stride = <0x0 0x20000>; /* 128KB stride */
156 #redistributor-regions = <1>;
157 interrupt-controller;
163 ap_clk: clock-controller@21500000 {
164 compatible = "sprd,sc9863a-ap-clk";
167 clock-names = "ext-32k", "ext-26m";
168 #clock-cells = <1>;
171 aon_clk: clock-controller@402d0000 {
172 compatible = "sprd,sc9863a-aon-clk";
176 clock-names = "ext-26m", "rco-100m",
177 "ext-32k", "ext-4m";
178 #clock-cells = <1>;
181 mm_clk: clock-controller@60900000 {
182 compatible = "sprd,sc9863a-mm-clk";
184 #clock-cells = <1>;
188 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
191 clock-names = "apb_pclk";
193 out-ports {
196 remote-endpoint = <&etb_in>;
201 in-ports {
204 remote-endpoint =
212 compatible = "arm,coresight-tmc", "arm,primecell";
215 clock-names = "apb_pclk";
217 in-ports {
220 remote-endpoint =
228 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
231 clock-names = "apb_pclk";
233 out-ports {
236 remote-endpoint =
242 in-ports {
243 #address-cells = <1>;
244 #size-cells = <0>;
249 remote-endpoint = <&etm0_out>;
256 remote-endpoint = <&etm1_out>;
263 remote-endpoint = <&etm2_out>;
270 remote-endpoint = <&etm3_out>;
277 compatible = "arm,coresight-tmc", "arm,primecell";
280 clock-names = "apb_pclk";
282 out-ports {
285 remote-endpoint =
291 in-port {
294 remote-endpoint =
302 compatible = "arm,coresight-tmc", "arm,primecell";
305 clock-names = "apb_pclk";
307 out-ports {
310 remote-endpoint =
316 in-ports {
319 remote-endpoint =
327 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
330 clock-names = "apb_pclk";
332 out-ports {
335 remote-endpoint =
341 in-ports {
342 #address-cells = <1>;
343 #size-cells = <0>;
348 remote-endpoint =
356 remote-endpoint =
364 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
367 clock-names = "apb_pclk";
369 out-ports {
372 remote-endpoint =
378 in-ports {
379 #address-cells = <1>;
380 #size-cells = <0>;
385 remote-endpoint = <&etm4_out>;
392 remote-endpoint = <&etm5_out>;
399 remote-endpoint = <&etm6_out>;
406 remote-endpoint = <&etm7_out>;
413 compatible = "arm,coresight-etm4x", "arm,primecell";
417 clock-names = "apb_pclk";
419 out-ports {
422 remote-endpoint =
430 compatible = "arm,coresight-etm4x", "arm,primecell";
434 clock-names = "apb_pclk";
436 out-ports {
439 remote-endpoint =
447 compatible = "arm,coresight-etm4x", "arm,primecell";
451 clock-names = "apb_pclk";
453 out-ports {
456 remote-endpoint =
464 compatible = "arm,coresight-etm4x", "arm,primecell";
468 clock-names = "apb_pclk";
470 out-ports {
473 remote-endpoint =
481 compatible = "arm,coresight-etm4x", "arm,primecell";
485 clock-names = "apb_pclk";
487 out-ports {
490 remote-endpoint =
498 compatible = "arm,coresight-etm4x", "arm,primecell";
502 clock-names = "apb_pclk";
504 out-ports {
507 remote-endpoint =
515 compatible = "arm,coresight-etm4x", "arm,primecell";
519 clock-names = "apb_pclk";
521 out-ports {
524 remote-endpoint =
532 compatible = "arm,coresight-etm4x", "arm,primecell";
536 clock-names = "apb_pclk";
538 out-ports {
541 remote-endpoint =
548 ap-ahb {
549 compatible = "simple-bus";
550 #address-cells = <2>;
551 #size-cells = <2>;
555 compatible = "sprd,sdhci-r11";
561 clock-names = "sdio", "enable";
562 assigned-clocks = <&aon_clk CLK_SDIO0_2X>;
563 assigned-clock-parents = <&rpll CLK_RPLL_390M>;
565 bus-width = <4>;
566 no-sdio;
567 no-mmc;
571 compatible = "sprd,sdhci-r11";
577 clock-names = "sdio", "enable";
578 assigned-clocks = <&aon_clk CLK_EMMC_2X>;
579 assigned-clock-parents = <&rpll CLK_RPLL_390M>;
581 bus-width = <8>;
582 non-removable;
583 no-sdio;
584 no-sd;
585 cap-mmc-hw-reset;