dts/sprd/sc9860.dtsi

16 		#size-cells = <0>;
53 			reg = <0x0 0x530000>;
61 			reg = <0x0 0x530001>;
69 			reg = <0x0 0x530002>;
77 			reg = <0x0 0x530003>;
85 			reg = <0x0 0x530100>;
93 			reg = <0x0 0x530101>;
101 			reg = <0x0 0x530102>;
109 			reg = <0x0 0x530103>;
124 			arm,psci-suspend-param = <0x00010002>;
133 			arm,psci-suspend-param = <0x01010003>;
177 			reg = <0 0x12001000 0 0x1000>,
178 			      <0 0x12002000 0 0x2000>,
179 			      <0 0x12004000 0 0x2000>,
180 			      <0 0x12006000 0 0x2000>;
189 			sprd,syscon = <&pmu_regs>; /* 0x402b0000 */
196 			sprd,syscon = <&ana_regs>; /* 0x40400000 */
197 			clocks = <&pmu_gate 0>;
203 			reg = <0 0x20000000 0 0x400>;
204 			clocks = <&ext_26m>, <&pll 0>,
205 				 <&pmu_gate 0>;
211 			reg = <0 0x402d0000 0 0x400>;
212 			clocks = <&ext_26m>, <&pll 0>,
213 				 <&pmu_gate 0>;
219 			sprd,syscon = <&ap_ahb_regs>; /* 0x20210000 */
220 			clocks = <&aon_prediv 0>;
226 			sprd,syscon = <&aon_regs>; /* 0x402e0000 */
227 			clocks = <&aon_prediv 0>;
233 			reg = <0 0x40880000 0 0x400>;
234 			clocks = <&ext_26m>, <&pll 0>;
240 			sprd,syscon = <&agcp_regs>; /* 0x415e0000 */
241 			clocks = <&aon_prediv 0>;
247 			reg = <0 0x60200000 0 0x400>;
248 			clocks = <&pll 0>;
254 			reg = <0 0x61000000 0 0x400>;
255 			clocks = <&ext_26m>, <&pll 0>;
261 			sprd,syscon = <&vsp_regs>; /* 0x61100000 */
262 			clocks = <&vsp_clk 0>;
268 			reg = <0 0x62000000 0 0x4000>;
269 			clocks = <&ext_26m>, <&pll 0>;
275 			sprd,syscon = <&cam_regs>; /* 0x62100000 */
276 			clocks = <&cam_clk 0>;
282 			reg = <0 0x63000000 0 0x400>;
283 			clocks = <&ext_26m>, <&pll 0>;
289 			sprd,syscon = <&disp_regs>; /* 0x63100000 */
290 			clocks = <&disp_clk 0>;
296 			sprd,syscon = <&ap_apb_regs>; /* 0x70b00000 */
297 			clocks = <&ap_clk 0>;
303 			reg = <0 0x10001000 0 0x1000>;
316 				#size-cells = <0>;
318 				port@0 {
319 					reg = <0>;
338 			reg = <0 0x10003000 0 0x1000>;
353 			reg = <0 0x10006000 0 0x1000>,
354 			      <0 0x01000000 0 0x180000>;
370 			reg = <0 0x11001000 0 0x1000>;
384 				#size-cells = <0>;
386 				port@0 {
387 					reg = <0>;
418 			reg = <0 0x11002000 0 0x1000>;
432 				#size-cells = <0>;
434 				port@0 {
435 					reg = <0>;
466 			reg = <0 0x11003000 0 0x1000>;
491 			reg = <0 0x11004000 0 0x1000>;
516 			reg = <0 0x11005000 0 0x1000>;
531 				#size-cells = <0>;
533 				port@0 {
534 					reg = <0>;
553 			reg = <0 0x11440000 0 0x1000>;
570 			reg = <0 0x11540000 0 0x1000>;
587 			reg = <0 0x11640000 0 0x1000>;
604 			reg = <0 0x11740000 0 0x1000>;
621 			reg = <0 0x11840000 0 0x1000>;
638 			reg = <0 0x11940000 0 0x1000>;
655 			reg = <0 0x11a40000 0 0x1000>;
672 			reg = <0 0x11b40000 0 0x1000>;