dts/sprd/sc9836.dtsi

1 // SPDX-License-Identifier: (GPL-2.0-only OR MIT)
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 		#address-cells = <2>;
16 		#size-cells = <0>;
20 			compatible = "arm,cortex-a53";
22 			enable-method = "psci";
27 			compatible = "arm,cortex-a53";
29 			enable-method = "psci";
34 			compatible = "arm,cortex-a53";
36 			enable-method = "psci";
41 			compatible = "arm,cortex-a53";
43 			enable-method = "psci";
48 		compatible = "arm,coresight-tmc", "arm,primecell";
51 		clock-names = "apb_pclk";
52 		in-ports {
55 					remote-endpoint = <&funnel_out_port0>;
62 		compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
65 		clock-names = "apb_pclk";
67 		out-ports {
70 					remote-endpoint = <&etf_in>;
75 		in-ports {
76 			#address-cells = <1>;
77 			#size-cells = <0>;
82 					remote-endpoint = <&etm0_out>;
89 					remote-endpoint = <&etm1_out>;
96 					remote-endpoint = <&etm2_out>;
103 					remote-endpoint = <&etm3_out>;
110 					remote-endpoint = <&stm_out>;
118 		compatible = "arm,coresight-etm4x", "arm,primecell";
123 		clock-names = "apb_pclk";
124 		out-ports {
127 					remote-endpoint = <&funnel_in_port0>;
134 		compatible = "arm,coresight-etm4x", "arm,primecell";
139 		clock-names = "apb_pclk";
140 		out-ports {
143 					remote-endpoint = <&funnel_in_port1>;
150 		compatible = "arm,coresight-etm4x", "arm,primecell";
155 		clock-names = "apb_pclk";
156 		out-ports {
159 					remote-endpoint = <&funnel_in_port2>;
166 		compatible = "arm,coresight-etm4x", "arm,primecell";
171 		clock-names = "apb_pclk";
172 		out-ports {
175 					remote-endpoint = <&funnel_in_port3>;
182 		compatible = "arm,coresight-stm", "arm,primecell";
185 		reg-names = "stm-base", "stm-stimulus-base";
187 		clock-names = "apb_pclk";
188 		out-ports {
191 					remote-endpoint = <&funnel_in_port4>;
197 	gic: interrupt-controller@12001000 {
198 		compatible = "arm,gic-400";
203 		#interrupt-cells = <3>;
204 		interrupt-controller;
217 		compatible = "arm,armv8-timer";