Lines Matching +full:0 +full:x40c00000
56 #size-cells = <0>;
91 cpu_l0: cpu@0 {
94 reg = <0x0>;
115 reg = <0x100>;
134 reg = <0x200>;
153 reg = <0x300>;
172 reg = <0x400>;
193 reg = <0x500>;
212 reg = <0x600>;
233 reg = <0x700>;
254 arm,psci-suspend-param = <0x0010000>;
368 arm,smc-id = <0x82000010>;
371 #size-cells = <0>;
374 reg = <0x14>;
379 reg = <0x16>;
400 spll: clock-0 {
404 #clock-cells = <0>;
409 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>,
410 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>,
411 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>,
412 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>,
413 <GIC_PPI 12 IRQ_TYPE_LEVEL_HIGH 0>;
421 #clock-cells = <0>;
428 #clock-cells = <0>;
433 reg = <0x0 0x0010f000 0x0 0x100>;
434 ranges = <0 0x0 0x0010f000 0x100>;
438 scmi_shmem: sram@0 {
440 reg = <0x0 0x100>;
446 reg = <0x0 0xfb000000 0x0 0x200000>;
454 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH 0>,
455 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH 0>,
456 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH 0>;
464 reg = <0x0 0xfc000000 0x0 0x400000>;
465 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 0>;
486 reg = <0x0 0xfc800000 0x0 0x40000>;
487 interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH 0>;
497 reg = <0x0 0xfc840000 0x0 0x40000>;
498 interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH 0>;
508 reg = <0x0 0xfc880000 0x0 0x40000>;
509 interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH 0>;
519 reg = <0x0 0xfc8c0000 0x0 0x40000>;
520 interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH 0>;
530 reg = <0x0 0xfcd00000 0x0 0x400000>;
531 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH 0>;
551 reg = <0x0 0xfc900000 0x0 0x200000>;
552 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH 0>,
553 <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH 0>,
554 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH 0>,
555 <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH 0>;
563 reg = <0x0 0xfcb00000 0x0 0x200000>;
564 interrupts = <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH 0>,
565 <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH 0>,
566 <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH 0>,
567 <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH 0>;
575 reg = <0x0 0xfd58a000 0x0 0x10000>;
580 reg = <0x0 0xfd58c000 0x0 0x1000>;
585 reg = <0x0 0xfd5a4000 0x0 0x2000>;
590 reg = <0x0 0xfd5a6000 0x0 0x2000>;
596 reg = <0x0 0xfd5a8000 0x0 0x4000>;
602 reg = <0x0 0xfd5ac000 0x0 0x4000>;
607 reg = <0x0 0xfd5b0000 0x0 0x1000>;
612 reg = <0x0 0xfd5bc000 0x0 0x100>;
617 reg = <0x0 0xfd5c4000 0x0 0x100>;
622 reg = <0x0 0xfd5c8000 0x0 0x4000>;
627 reg = <0x0 0xfd5d0000 0x0 0x4000>;
631 u2phy0: usb2phy@0 {
633 reg = <0x0 0x10>;
634 #clock-cells = <0>;
638 interrupts = <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH 0>;
644 #phy-cells = <0>;
652 reg = <0x0 0xfd5d8000 0x0 0x4000>;
658 reg = <0x8000 0x10>;
659 #clock-cells = <0>;
663 interrupts = <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH 0>;
669 #phy-cells = <0>;
677 reg = <0x0 0xfd5dc000 0x0 0x4000>;
683 reg = <0xc000 0x10>;
684 #clock-cells = <0>;
688 interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH 0>;
694 #phy-cells = <0>;
702 reg = <0x0 0xfd5e0000 0x0 0x100>;
707 reg = <0x0 0xfd5f0000 0x0 0x10000>;
712 reg = <0x0 0xfd600000 0x0 0x100000>;
713 ranges = <0x0 0x0 0xfd600000 0x100000>;
720 reg = <0x0 0xfd7c0000 0x0 0x5c000>;
748 reg = <0x0 0xfd880000 0x0 0x1000>;
749 interrupts = <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH 0>;
752 pinctrl-0 = <&i2c0m0_xfer>;
755 #size-cells = <0>;
761 reg = <0x0 0xfd890000 0x0 0x100>;
762 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH 0>;
767 pinctrl-0 = <&uart0m1_xfer>;
776 reg = <0x0 0xfd8b0000 0x0 0x10>;
779 pinctrl-0 = <&pwm0m0_pins>;
787 reg = <0x0 0xfd8b0010 0x0 0x10>;
790 pinctrl-0 = <&pwm1m0_pins>;
798 reg = <0x0 0xfd8b0020 0x0 0x10>;
801 pinctrl-0 = <&pwm2m0_pins>;
809 reg = <0x0 0xfd8b0030 0x0 0x10>;
812 pinctrl-0 = <&pwm3m0_pins>;
820 reg = <0x0 0xfd8d8000 0x0 0x400>;
826 #size-cells = <0>;
832 #power-domain-cells = <0>;
834 #size-cells = <0>;
845 #power-domain-cells = <0>;
847 #size-cells = <0>;
855 #power-domain-cells = <0>;
863 #power-domain-cells = <0>;
877 #power-domain-cells = <0>;
883 #size-cells = <0>;
884 #power-domain-cells = <0>;
894 #power-domain-cells = <0>;
903 #power-domain-cells = <0>;
913 #size-cells = <0>;
914 #power-domain-cells = <0>;
925 #power-domain-cells = <0>;
959 #size-cells = <0>;
960 #power-domain-cells = <0>;
969 #power-domain-cells = <0>;
978 #power-domain-cells = <0>;
986 #power-domain-cells = <0>;
993 #power-domain-cells = <0>;
1004 #size-cells = <0>;
1005 #power-domain-cells = <0>;
1017 #power-domain-cells = <0>;
1031 #power-domain-cells = <0>;
1046 #size-cells = <0>;
1047 #power-domain-cells = <0>;
1057 #power-domain-cells = <0>;
1068 #power-domain-cells = <0>;
1076 #power-domain-cells = <0>;
1092 #power-domain-cells = <0>;
1099 #power-domain-cells = <0>;
1106 #power-domain-cells = <0>;
1113 #power-domain-cells = <0>;
1119 #power-domain-cells = <0>;
1124 #power-domain-cells = <0>;
1131 reg = <0x0 0xfdb50000 0x0 0x800>;
1132 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
1142 reg = <0x0 0xfdb50800 0x0 0x40>;
1143 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
1147 #iommu-cells = <0>;
1152 reg = <0x0 0xfdb80000 0x0 0x180>;
1153 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>;
1163 reg = <0x0 0xfdba0000 0x0 0x800>;
1164 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH 0>;
1173 reg = <0x0 0xfdba0800 0x0 0x40>;
1174 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH 0>;
1178 #iommu-cells = <0>;
1183 reg = <0x0 0xfdba4000 0x0 0x800>;
1184 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH 0>;
1193 reg = <0x0 0xfdba4800 0x0 0x40>;
1194 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH 0>;
1198 #iommu-cells = <0>;
1203 reg = <0x0 0xfdba8000 0x0 0x800>;
1204 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH 0>;
1213 reg = <0x0 0xfdba8800 0x0 0x40>;
1214 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH 0>;
1218 #iommu-cells = <0>;
1223 reg = <0x0 0xfdbac000 0x0 0x800>;
1224 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH 0>;
1233 reg = <0x0 0xfdbac800 0x0 0x40>;
1234 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH 0>;
1238 #iommu-cells = <0>;
1243 reg = <0x0 0xfdc70000 0x0 0x800>;
1244 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>;
1256 reg = <0x0 0xfdd90000 0x0 0x4200>, <0x0 0xfdd95000 0x0 0x1000>;
1258 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH 0>;
1283 #size-cells = <0>;
1285 vp0: port@0 {
1287 #size-cells = <0>;
1288 reg = <0>;
1293 #size-cells = <0>;
1299 #size-cells = <0>;
1305 #size-cells = <0>;
1313 reg = <0x0 0xfdd97e00 0x0 0x100>, <0x0 0xfdd97f00 0x0 0x100>;
1314 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH 0>;
1317 #iommu-cells = <0>;
1324 reg = <0x0 0xfddc0000 0x0 0x1000>;
1325 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH 0>;
1330 dmas = <&dmac2 0>;
1335 #sound-dai-cells = <0>;
1341 reg = <0x0 0xfddf0000 0x0 0x1000>;
1342 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH 0>;
1352 #sound-dai-cells = <0>;
1358 reg = <0x0 0xfddfc000 0x0 0x1000>;
1359 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH 0>;
1369 #sound-dai-cells = <0>;
1375 reg = <0x0 0xfdf35000 0x0 0x20>;
1380 reg = <0x0 0xfdf35200 0x0 0x20>;
1385 reg = <0x0 0xfdf35400 0x0 0x20>;
1390 reg = <0x0 0xfdf35600 0x0 0x20>;
1395 reg = <0x0 0xfdf36000 0x0 0x20>;
1400 reg = <0x0 0xfdf39000 0x0 0x20>;
1405 reg = <0x0 0xfdf3d800 0x0 0x20>;
1410 reg = <0x0 0xfdf3e000 0x0 0x20>;
1415 reg = <0x0 0xfdf3e200 0x0 0x20>;
1420 reg = <0x0 0xfdf3e400 0x0 0x20>;
1425 reg = <0x0 0xfdf3e600 0x0 0x20>;
1430 reg = <0x0 0xfdf40000 0x0 0x20>;
1435 reg = <0x0 0xfdf40200 0x0 0x20>;
1440 reg = <0x0 0xfdf40400 0x0 0x20>;
1445 reg = <0x0 0xfdf40500 0x0 0x20>;
1450 reg = <0x0 0xfdf40600 0x0 0x20>;
1455 reg = <0x0 0xfdf40800 0x0 0x20>;
1460 reg = <0x0 0xfdf41000 0x0 0x20>;
1465 reg = <0x0 0xfdf41100 0x0 0x20>;
1470 reg = <0x0 0xfdf60000 0x0 0x20>;
1475 reg = <0x0 0xfdf60200 0x0 0x20>;
1480 reg = <0x0 0xfdf60400 0x0 0x20>;
1485 reg = <0x0 0xfdf61000 0x0 0x20>;
1490 reg = <0x0 0xfdf61200 0x0 0x20>;
1495 reg = <0x0 0xfdf61400 0x0 0x20>;
1500 reg = <0x0 0xfdf62000 0x0 0x20>;
1505 reg = <0x0 0xfdf63000 0x0 0x20>;
1510 reg = <0x0 0xfdf64000 0x0 0x20>;
1515 reg = <0x0 0xfdf66000 0x0 0x20>;
1520 reg = <0x0 0xfdf66200 0x0 0x20>;
1525 reg = <0x0 0xfdf66400 0x0 0x20>;
1530 reg = <0x0 0xfdf66600 0x0 0x20>;
1535 reg = <0x0 0xfdf66800 0x0 0x20>;
1540 reg = <0x0 0xfdf66a00 0x0 0x20>;
1545 reg = <0x0 0xfdf66c00 0x0 0x20>;
1550 reg = <0x0 0xfdf66e00 0x0 0x20>;
1555 reg = <0x0 0xfdf67000 0x0 0x20>;
1560 reg = <0x0 0xfdf67200 0x0 0x20>;
1565 reg = <0x0 0xfdf70000 0x0 0x20>;
1570 reg = <0x0 0xfdf71000 0x0 0x20>;
1575 reg = <0x0 0xfdf72000 0x0 0x20>;
1580 reg = <0x0 0xfdf72200 0x0 0x20>;
1585 reg = <0x0 0xfdf72400 0x0 0x20>;
1590 reg = <0x0 0xfdf80000 0x0 0x20>;
1595 reg = <0x0 0xfdf81000 0x0 0x20>;
1600 reg = <0x0 0xfdf81200 0x0 0x20>;
1605 reg = <0x0 0xfdf82000 0x0 0x20>;
1610 reg = <0x0 0xfdf82200 0x0 0x20>;
1614 reg = <0x00 0xfe060000 0x00 0x10000>;
1616 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>,
1617 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>,
1618 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH 0>,
1619 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>;
1625 bus-range = <0x30 0x3f>;
1633 interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH 0>,
1634 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH 0>,
1635 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH 0>,
1636 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH 0>,
1637 <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH 0>;
1640 interrupt-map-mask = <0 0 0 7>;
1641 interrupt-map = <0 0 0 1 &pcie2x1l1_intc 0>,
1642 <0 0 0 2 &pcie2x1l1_intc 1>,
1643 <0 0 0 3 &pcie2x1l1_intc 2>,
1644 <0 0 0 4 &pcie2x1l1_intc 3>;
1647 msi-map = <0x3000 &its0 0x3000 0x1000>;
1652 ranges = <0x01000000 0x0 0xf3100000 0x0 0xf3100000 0x0 0x00100000>,
1653 <0x02000000 0x0 0xf3200000 0x0 0xf3200000 0x0 0x00e00000>,
1654 <0x03000000 0x0 0x40000000 0x9 0xc0000000 0x0 0x40000000>;
1655 reg = <0xa 0x40c00000 0x0 0x00400000>,
1656 <0x0 0xfe180000 0x0 0x00010000>,
1657 <0x0 0xf3000000 0x0 0x00100000>;
1667 #address-cells = <0>;
1670 interrupts = <GIC_SPI 245 IRQ_TYPE_EDGE_RISING 0>;
1676 bus-range = <0x40 0x4f>;
1684 interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH 0>,
1685 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>,
1686 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH 0>,
1687 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH 0>,
1688 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH 0>;
1691 interrupt-map-mask = <0 0 0 7>;
1692 interrupt-map = <0 0 0 1 &pcie2x1l2_intc 0>,
1693 <0 0 0 2 &pcie2x1l2_intc 1>,
1694 <0 0 0 3 &pcie2x1l2_intc 2>,
1695 <0 0 0 4 &pcie2x1l2_intc 3>;
1698 msi-map = <0x4000 &its0 0x4000 0x1000>;
1703 ranges = <0x01000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x00100000>,
1704 <0x02000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x00e00000>,
1705 <0x03000000 0x0 0x40000000 0xa 0x00000000 0x0 0x40000000>;
1706 reg = <0xa 0x41000000 0x0 0x00400000>,
1707 <0x0 0xfe190000 0x0 0x00010000>,
1708 <0x0 0xf4000000 0x0 0x00100000>;
1718 #address-cells = <0>;
1721 interrupts = <GIC_SPI 250 IRQ_TYPE_EDGE_RISING 0>;
1727 reg = <0x0 0xfe1c0000 0x0 0x10000>;
1728 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH 0>,
1729 <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH 0>;
1751 #address-cells = <0x1>;
1752 #size-cells = <0x0>;
1756 snps,blen = <0 0 0 0 16 8 4>;
1776 reg = <0 0xfe210000 0 0x1000>;
1777 interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH 0>;
1782 ports-implemented = <0x1>;
1784 #size-cells = <0>;
1787 sata-port@0 {
1788 reg = <0>;
1799 reg = <0 0xfe230000 0 0x1000>;
1800 interrupts = <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH 0>;
1805 ports-implemented = <0x1>;
1807 #size-cells = <0>;
1810 sata-port@0 {
1811 reg = <0>;
1822 reg = <0x0 0xfe2b0000 0x0 0x4000>;
1823 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH 0>;
1827 #size-cells = <0>;
1833 reg = <0x0 0xfe2c0000 0x0 0x4000>;
1834 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH 0>;
1838 fifo-depth = <0x100>;
1841 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>;
1848 reg = <0x00 0xfe2d0000 0x00 0x4000>;
1849 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH 0>;
1853 fifo-depth = <0x100>;
1856 pinctrl-0 = <&sdiom1_pins>;
1863 reg = <0x0 0xfe2e0000 0x0 0x10000>;
1864 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH 0>;
1872 pinctrl-0 = <&emmc_rstnout>, <&emmc_bus8>, <&emmc_clk>,
1884 reg = <0x0 0xfe470000 0x0 0x1000>;
1885 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH 0>;
1890 dmas = <&dmac0 0>, <&dmac0 1>;
1897 pinctrl-0 = <&i2s0_lrck
1907 #sound-dai-cells = <0>;
1913 reg = <0x0 0xfe480000 0x0 0x1000>;
1914 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH 0>;
1923 pinctrl-0 = <&i2s1m0_lrck
1933 #sound-dai-cells = <0>;
1939 reg = <0x0 0xfe490000 0x0 0x1000>;
1940 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH 0>;
1945 dmas = <&dmac1 0>, <&dmac1 1>;
1949 pinctrl-0 = <&i2s2m1_lrck
1953 #sound-dai-cells = <0>;
1959 reg = <0x0 0xfe4a0000 0x0 0x1000>;
1960 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH 0>;
1969 pinctrl-0 = <&i2s3_lrck
1973 #sound-dai-cells = <0>;
1979 reg = <0x0 0xfe600000 0 0x10000>, /* GICD */
1980 <0x0 0xfe680000 0 0x100000>; /* GICR */
1981 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
1983 mbi-alias = <0x0 0xfe610000>;
1993 reg = <0x0 0xfe640000 0x0 0x20000>;
2000 reg = <0x0 0xfe660000 0x0 0x20000>;
2006 ppi_partition0: interrupt-partition-0 {
2018 reg = <0x0 0xfea10000 0x0 0x4000>;
2019 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH 0>,
2020 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH 0>;
2029 reg = <0x0 0xfea30000 0x0 0x4000>;
2030 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH 0>,
2031 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH 0>;
2040 reg = <0x0 0xfea90000 0x0 0x1000>;
2043 interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH 0>;
2044 pinctrl-0 = <&i2c1m0_xfer>;
2047 #size-cells = <0>;
2053 reg = <0x0 0xfeaa0000 0x0 0x1000>;
2056 interrupts = <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH 0>;
2057 pinctrl-0 = <&i2c2m0_xfer>;
2060 #size-cells = <0>;
2066 reg = <0x0 0xfeab0000 0x0 0x1000>;
2069 interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH 0>;
2070 pinctrl-0 = <&i2c3m0_xfer>;
2073 #size-cells = <0>;
2079 reg = <0x0 0xfeac0000 0x0 0x1000>;
2082 interrupts = <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH 0>;
2083 pinctrl-0 = <&i2c4m0_xfer>;
2086 #size-cells = <0>;
2092 reg = <0x0 0xfead0000 0x0 0x1000>;
2095 interrupts = <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH 0>;
2096 pinctrl-0 = <&i2c5m0_xfer>;
2099 #size-cells = <0>;
2105 reg = <0x0 0xfeae0000 0x0 0x20>;
2106 interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH 0>;
2113 reg = <0x0 0xfeaf0000 0x0 0x100>;
2116 interrupts = <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH 0>;
2121 reg = <0x0 0xfeb00000 0x0 0x1000>;
2122 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH 0>;
2128 pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>;
2131 #size-cells = <0>;
2137 reg = <0x0 0xfeb10000 0x0 0x1000>;
2138 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH 0>;
2144 pinctrl-0 = <&spi1m1_cs0 &spi1m1_cs1 &spi1m1_pins>;
2147 #size-cells = <0>;
2153 reg = <0x0 0xfeb20000 0x0 0x1000>;
2154 interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH 0>;
2160 pinctrl-0 = <&spi2m2_cs0 &spi2m2_cs1 &spi2m2_pins>;
2163 #size-cells = <0>;
2169 reg = <0x0 0xfeb30000 0x0 0x1000>;
2170 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH 0>;
2176 pinctrl-0 = <&spi3m1_cs0 &spi3m1_cs1 &spi3m1_pins>;
2179 #size-cells = <0>;
2185 reg = <0x0 0xfeb40000 0x0 0x100>;
2186 interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH 0>;
2191 pinctrl-0 = <&uart1m1_xfer>;
2200 reg = <0x0 0xfeb50000 0x0 0x100>;
2201 interrupts = <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH 0>;
2206 pinctrl-0 = <&uart2m1_xfer>;
2215 reg = <0x0 0xfeb60000 0x0 0x100>;
2216 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH 0>;
2221 pinctrl-0 = <&uart3m1_xfer>;
2230 reg = <0x0 0xfeb70000 0x0 0x100>;
2231 interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH 0>;
2236 pinctrl-0 = <&uart4m1_xfer>;
2245 reg = <0x0 0xfeb80000 0x0 0x100>;
2246 interrupts = <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH 0>;
2251 pinctrl-0 = <&uart5m1_xfer>;
2260 reg = <0x0 0xfeb90000 0x0 0x100>;
2261 interrupts = <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH 0>;
2266 pinctrl-0 = <&uart6m1_xfer>;
2275 reg = <0x0 0xfeba0000 0x0 0x100>;
2276 interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH 0>;
2281 pinctrl-0 = <&uart7m1_xfer>;
2290 reg = <0x0 0xfebb0000 0x0 0x100>;
2291 interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH 0>;
2296 pinctrl-0 = <&uart8m1_xfer>;
2305 reg = <0x0 0xfebc0000 0x0 0x100>;
2306 interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH 0>;
2311 pinctrl-0 = <&uart9m1_xfer>;
2320 reg = <0x0 0xfebd0000 0x0 0x10>;
2323 pinctrl-0 = <&pwm4m0_pins>;
2331 reg = <0x0 0xfebd0010 0x0 0x10>;
2334 pinctrl-0 = <&pwm5m0_pins>;
2342 reg = <0x0 0xfebd0020 0x0 0x10>;
2345 pinctrl-0 = <&pwm6m0_pins>;
2353 reg = <0x0 0xfebd0030 0x0 0x10>;
2356 pinctrl-0 = <&pwm7m0_pins>;
2364 reg = <0x0 0xfebe0000 0x0 0x10>;
2367 pinctrl-0 = <&pwm8m0_pins>;
2375 reg = <0x0 0xfebe0010 0x0 0x10>;
2378 pinctrl-0 = <&pwm9m0_pins>;
2386 reg = <0x0 0xfebe0020 0x0 0x10>;
2389 pinctrl-0 = <&pwm10m0_pins>;
2397 reg = <0x0 0xfebe0030 0x0 0x10>;
2400 pinctrl-0 = <&pwm11m0_pins>;
2408 reg = <0x0 0xfebf0000 0x0 0x10>;
2411 pinctrl-0 = <&pwm12m0_pins>;
2419 reg = <0x0 0xfebf0010 0x0 0x10>;
2422 pinctrl-0 = <&pwm13m0_pins>;
2430 reg = <0x0 0xfebf0020 0x0 0x10>;
2433 pinctrl-0 = <&pwm14m0_pins>;
2441 reg = <0x0 0xfebf0030 0x0 0x10>;
2444 pinctrl-0 = <&pwm15m0_pins>;
2453 polling-delay-passive = <0>;
2454 polling-delay = <0>;
2455 thermal-sensors = <&tsadc 0>;
2460 hysteresis = <0>;
2466 /* sensor between A76 cores 0 and 1 */
2469 polling-delay = <0>;
2481 hysteresis = <0>;
2499 polling-delay = <0>;
2511 hysteresis = <0>;
2529 polling-delay = <0>;
2541 hysteresis = <0>;
2560 polling-delay-passive = <0>;
2561 polling-delay = <0>;
2567 hysteresis = <0>;
2575 polling-delay = <0>;
2587 hysteresis = <0>;
2602 polling-delay-passive = <0>;
2603 polling-delay = <0>;
2609 hysteresis = <0>;
2618 reg = <0x0 0xfec00000 0x0 0x400>;
2619 interrupts = <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH 0>;
2627 rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */
2628 rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */
2629 pinctrl-0 = <&tsadc_gpio_func>;
2638 reg = <0x0 0xfec10000 0x0 0x10000>;
2639 interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH 0>;
2650 reg = <0x0 0xfec80000 0x0 0x1000>;
2653 interrupts = <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH 0>;
2654 pinctrl-0 = <&i2c6m0_xfer>;
2657 #size-cells = <0>;
2663 reg = <0x0 0xfec90000 0x0 0x1000>;
2666 interrupts = <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH 0>;
2667 pinctrl-0 = <&i2c7m0_xfer>;
2670 #size-cells = <0>;
2676 reg = <0x0 0xfeca0000 0x0 0x1000>;
2679 interrupts = <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH 0>;
2680 pinctrl-0 = <&i2c8m0_xfer>;
2683 #size-cells = <0>;
2689 reg = <0x0 0xfecb0000 0x0 0x1000>;
2690 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH 0>;
2696 pinctrl-0 = <&spi4m0_cs0 &spi4m0_cs1 &spi4m0_pins>;
2699 #size-cells = <0>;
2705 reg = <0x0 0xfecc0000 0x0 0x400>;
2716 reg = <0x02 0x2>;
2720 reg = <0x07 0x10>;
2724 reg = <0x17 0x1>;
2728 reg = <0x18 0x1>;
2732 reg = <0x19 0x1>;
2736 reg = <0x1a 0x1>;
2740 reg = <0x1b 0x1>;
2744 reg = <0x1c 0x1>;
2749 reg = <0x28 0x1>;
2753 reg = <0x29 0x1>;
2759 reg = <0x0 0xfed10000 0x0 0x4000>;
2760 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH 0>,
2761 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH 0>;
2770 reg = <0x0 0xfed60000 0x0 0x2000>;
2773 #phy-cells = <0>;
2786 reg = <0x0 0xfed80000 0x0 0x10000>;
2808 reg = <0x0 0xfee00000 0x0 0x100>;
2824 reg = <0x0 0xfee20000 0x0 0x100>;
2840 reg = <0x0 0xff001000 0x0 0xef000>;
2841 ranges = <0x0 0x0 0xff001000 0xef000>;
2855 reg = <0x0 0xfd8a0000 0x0 0x100>;
2856 interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH 0>;
2859 gpio-ranges = <&pinctrl 0 0 32>;
2867 reg = <0x0 0xfec20000 0x0 0x100>;
2868 interrupts = <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH 0>;
2871 gpio-ranges = <&pinctrl 0 32 32>;
2879 reg = <0x0 0xfec30000 0x0 0x100>;
2880 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH 0>;
2883 gpio-ranges = <&pinctrl 0 64 32>;
2891 reg = <0x0 0xfec40000 0x0 0x100>;
2892 interrupts = <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH 0>;
2895 gpio-ranges = <&pinctrl 0 96 32>;
2903 reg = <0x0 0xfec50000 0x0 0x100>;
2904 interrupts = <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH 0>;
2907 gpio-ranges = <&pinctrl 0 128 32>;