Lines Matching +full:cru +full:- +full:bus
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
12 compatible = "rockchip,rk3568-dwc-ahci", "snps,dwc-ahci";
14 clocks = <&cru ACLK_SATA0>, <&cru CLK_SATA0_PMALIVE>,
15 <&cru CLK_SATA0_RXOOB>;
16 clock-names = "sata", "pmalive", "rxoob";
19 phy-names = "sata-phy";
20 ports-implemented = <0x1>;
21 power-domains = <&power RK3568_PD_PIPE>;
26 compatible = "rockchip,rk3568-pipe-phy-grf", "syscon";
31 compatible = "rockchip,rk3568-qos", "syscon";
36 compatible = "rockchip,rk3568-qos", "syscon";
41 compatible = "rockchip,rk3568-qos", "syscon";
46 compatible = "rockchip,rk3568-pcie3-phy-grf", "syscon";
51 compatible = "rockchip,rk3568-pcie3-phy";
53 #phy-cells = <0>;
55 <&cru PCLK_PCIE30PHY>;
56 clock-names = "refclk_m", "refclk_n", "pclk";
57 resets = <&cru SRST_PCIE30PHY>;
58 reset-names = "phy";
59 rockchip,phy-grf = <&pcie30_phy_grf>;
64 compatible = "rockchip,rk3568-pcie";
65 #address-cells = <3>;
66 #size-cells = <2>;
67 bus-range = <0x0 0xf>;
68 clocks = <&cru ACLK_PCIE30X1_MST>, <&cru ACLK_PCIE30X1_SLV>,
69 <&cru ACLK_PCIE30X1_DBI>, <&cru PCLK_PCIE30X1>,
70 <&cru CLK_PCIE30X1_AUX_NDFT>;
71 clock-names = "aclk_mst", "aclk_slv",
79 interrupt-names = "sys", "pmc", "msg", "legacy", "err";
80 #interrupt-cells = <1>;
81 interrupt-map-mask = <0 0 0 7>;
82 interrupt-map = <0 0 0 1 &pcie3x1_intc 0>,
86 linux,pci-domain = <1>;
87 num-ib-windows = <6>;
88 num-ob-windows = <2>;
89 max-link-speed = <3>;
90 msi-map = <0x0 &gic 0x1000 0x1000>;
91 num-lanes = <1>;
93 phy-names = "pcie-phy";
94 power-domains = <&power RK3568_PD_PIPE>;
101 reg-names = "dbi", "apb", "config";
102 resets = <&cru SRST_PCIE30X1_POWERUP>;
103 reset-names = "pipe";
107 pcie3x1_intc: legacy-interrupt-controller {
108 interrupt-controller;
109 #address-cells = <0>;
110 #interrupt-cells = <1>;
111 interrupt-parent = <&gic>;
117 compatible = "rockchip,rk3568-pcie";
118 #address-cells = <3>;
119 #size-cells = <2>;
120 bus-range = <0x0 0xf>;
121 clocks = <&cru ACLK_PCIE30X2_MST>, <&cru ACLK_PCIE30X2_SLV>,
122 <&cru ACLK_PCIE30X2_DBI>, <&cru PCLK_PCIE30X2>,
123 <&cru CLK_PCIE30X2_AUX_NDFT>;
124 clock-names = "aclk_mst", "aclk_slv",
132 interrupt-names = "sys", "pmc", "msg", "legacy", "err";
133 #interrupt-cells = <1>;
134 interrupt-map-mask = <0 0 0 7>;
135 interrupt-map = <0 0 0 1 &pcie3x2_intc 0>,
139 linux,pci-domain = <2>;
140 num-ib-windows = <6>;
141 num-ob-windows = <2>;
142 max-link-speed = <3>;
143 msi-map = <0x0 &gic 0x2000 0x1000>;
144 num-lanes = <2>;
146 phy-names = "pcie-phy";
147 power-domains = <&power RK3568_PD_PIPE>;
154 reg-names = "dbi", "apb", "config";
155 resets = <&cru SRST_PCIE30X2_POWERUP>;
156 reset-names = "pipe";
160 pcie3x2_intc: legacy-interrupt-controller {
161 interrupt-controller;
162 #address-cells = <0>;
163 #interrupt-cells = <1>;
164 interrupt-parent = <&gic>;
170 compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a";
174 interrupt-names = "macirq", "eth_wake_irq";
175 clocks = <&cru SCLK_GMAC0>, <&cru SCLK_GMAC0_RX_TX>,
176 <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_MAC0_REFOUT>,
177 <&cru ACLK_GMAC0>, <&cru PCLK_GMAC0>,
178 <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_GMAC0_PTP_REF>;
179 clock-names = "stmmaceth", "mac_clk_rx",
183 resets = <&cru SRST_A_GMAC0>;
184 reset-names = "stmmaceth";
186 snps,axi-config = <&gmac0_stmmac_axi_setup>;
187 snps,mixed-burst;
188 snps,mtl-rx-config = <&gmac0_mtl_rx_setup>;
189 snps,mtl-tx-config = <&gmac0_mtl_tx_setup>;
194 compatible = "snps,dwmac-mdio";
195 #address-cells = <0x1>;
196 #size-cells = <0x0>;
199 gmac0_stmmac_axi_setup: stmmac-axi-config {
205 gmac0_mtl_rx_setup: rx-queues-config {
206 snps,rx-queues-to-use = <1>;
210 gmac0_mtl_tx_setup: tx-queues-config {
211 snps,tx-queues-to-use = <1>;
217 compatible = "rockchip,rk3568v2-canfd";
220 clocks = <&cru CLK_CAN0>, <&cru PCLK_CAN0>;
221 clock-names = "baud", "pclk";
222 resets = <&cru SRST_CAN0>, <&cru SRST_P_CAN0>;
223 reset-names = "core", "apb";
224 pinctrl-names = "default";
225 pinctrl-0 = <&can0m0_pins>;
230 compatible = "rockchip,rk3568v2-canfd";
233 clocks = <&cru CLK_CAN1>, <&cru PCLK_CAN1>;
234 clock-names = "baud", "pclk";
235 resets = <&cru SRST_CAN1>, <&cru SRST_P_CAN1>;
236 reset-names = "core", "apb";
237 pinctrl-names = "default";
238 pinctrl-0 = <&can1m0_pins>;
243 compatible = "rockchip,rk3568v2-canfd";
246 clocks = <&cru CLK_CAN2>, <&cru PCLK_CAN2>;
247 clock-names = "baud", "pclk";
248 resets = <&cru SRST_CAN2>, <&cru SRST_P_CAN2>;
249 reset-names = "core", "apb";
250 pinctrl-names = "default";
251 pinctrl-0 = <&can2m0_pins>;
256 compatible = "rockchip,rk3568-naneng-combphy";
259 <&cru PCLK_PIPEPHY0>,
260 <&cru PCLK_PIPE>;
261 clock-names = "ref", "apb", "pipe";
262 assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>;
263 assigned-clock-rates = <100000000>;
264 resets = <&cru SRST_PIPEPHY0>;
265 rockchip,pipe-grf = <&pipegrf>;
266 rockchip,pipe-phy-grf = <&pipe_phy_grf0>;
267 #phy-cells = <1>;
273 opp-1992000000 {
274 opp-hz = /bits/ 64 <1992000000>;
275 opp-microvolt = <1150000 1150000 1150000>;
280 compatible = "rockchip,rk3568-pipe-grf", "syscon";
284 power-domain@RK3568_PD_PIPE {
286 clocks = <&cru PCLK_PIPE>;
295 #power-domain-cells = <0>;
305 phy-names = "usb2-phy", "usb3-phy";
309 compatible = "rockchip,rk3568-vop";