dts/rockchip/rk3568-radxa-e25.dts

1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 /dts-v1/;
4 #include "rk3568-radxa-cm3i.dtsi"
14 	pwm-leds {
15 		compatible = "pwm-leds-multicolor";
17 		multi-led {
19 			max-brightness = <255>;
21 			led-red {
26 			led-green {
31 			led-blue {
38 	vbus_typec: vbus-typec-regulator {
39 		compatible = "regulator-fixed";
40 		enable-active-high;
42 		pinctrl-names = "default";
43 		pinctrl-0 = <&vbus_typec_en>;
44 		regulator-name = "vbus_typec";
45 		regulator-min-microvolt = <5000000>;
46 		regulator-max-microvolt = <5000000>;
47 		vin-supply = <&vcc5v0_sys>;
53 	vcc3v3_minipcie: vcc3v3-minipcie-regulator {
54 		compatible = "regulator-fixed";
55 		enable-active-high;
57 		pinctrl-names = "default";
58 		pinctrl-0 = <&minipcie_enable_h>;
59 		regulator-name = "vcc3v3_minipcie";
60 		regulator-min-microvolt = <3300000>;
61 		regulator-max-microvolt = <3300000>;
62 		vin-supply = <&vcc3v3_pi6c_05>;
65 	vcc3v3_ngff: vcc3v3-ngff-regulator {
66 		compatible = "regulator-fixed";
67 		enable-active-high;
69 		pinctrl-names = "default";
70 		pinctrl-0 = <&ngffpcie_enable_h>;
71 		regulator-name = "vcc3v3_ngff";
72 		regulator-min-microvolt = <3300000>;
73 		regulator-max-microvolt = <3300000>;
74 		vin-supply = <&vcc5v0_sys>;
77 	vcc3v3_pcie30x1: vcc3v3-pcie30x1-regulator {
78 		compatible = "regulator-fixed";
79 		enable-active-high;
81 		pinctrl-names = "default";
82 		pinctrl-0 = <&pcie30x1_enable_h>;
83 		regulator-name = "vcc3v3_pcie30x1";
84 		regulator-min-microvolt = <3300000>;
85 		regulator-max-microvolt = <3300000>;
86 		vin-supply = <&vcc5v0_sys>;
89 	vcc3v3_pi6c_05: vcc3v3-pi6c-05-regulator {
90 		compatible = "regulator-fixed";
91 		enable-active-high;
93 		pinctrl-names = "default";
94 		pinctrl-0 = <&pcie_enable_h>;
95 		regulator-name = "vcc3v3_pcie";
96 		regulator-min-microvolt = <3300000>;
97 		regulator-max-microvolt = <3300000>;
98 		vin-supply = <&vcc5v0_sys>;
103 	phy-supply = <&vcc3v3_pcie30x1>;
111 	pinctrl-names = "default";
112 	pinctrl-0 = <&pcie20_reset_h>;
113 	reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>;
114 	vpcie3v3-supply = <&vcc3v3_pi6c_05>;
119 	data-lanes = <1 2>;
124 	num-lanes = <1>;
125 	pinctrl-names = "default";
126 	pinctrl-0 = <&pcie30x1m0_pins>;
127 	reset-gpios = <&gpio0 RK_PC3 GPIO_ACTIVE_HIGH>;
128 	vpcie3v3-supply = <&vcc3v3_minipcie>;
133 	num-lanes = <1>;
134 	pinctrl-names = "default";
135 	pinctrl-0 = <&pcie30x2_reset_h>;
136 	reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
137 	vpcie3v3-supply = <&vcc3v3_pi6c_05>;
143 		pcie20_reset_h: pcie20-reset-h {
147 		pcie30x1_enable_h: pcie30x1-enable-h {
151 		pcie30x2_reset_h: pcie30x2-reset-h {
155 		pcie_enable_h: pcie-enable-h {
161 		minipcie_enable_h: minipcie-enable-h {
165 		ngffpcie_enable_h: ngffpcie-enable-h {
184 	pinctrl-names = "default";
185 	pinctrl-0 = <&pwm12m1_pins>;
194 	bus-width = <4>;
195 	cap-sd-highspeed;
196 	cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
198 	disable-wp;
199 	pinctrl-names = "default";
200 	pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd>;
201 	sd-uhs-sdr104;
202 	vmmc-supply = <&vcc3v3_sd>;
203 	vqmmc-supply = <&vccio_sd>;
228 	phy-supply = <&vbus_typec>;
233 	phy-supply = <&vcc3v3_minipcie>;
238 	phy-supply = <&vcc3v3_ngff>;