dts/rockchip/rk3568-nanopi-r5s.dts

1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
9 /dts-v1/;
10 #include "rk3568-nanopi-r5s.dtsi"
14 	compatible = "friendlyarm,nanopi-r5s", "rockchip,rk3568";
20 	gpio-leds {
21 		compatible = "gpio-leds";
22 		pinctrl-names = "default";
23 		pinctrl-0 = <&lan1_led_pin>, <&lan2_led_pin>, <&power_led_pin>, <&wan_led_pin>;
25 		led-lan1 {
28 			function-enumerator = <1>;
32 		led-lan2 {
35 			function-enumerator = <2>;
39 		power_led: led-power {
42 			linux,default-trigger = "heartbeat";
46 		led-wan {
55 	assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
56 	assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>;
57 	assigned-clock-rates = <0>, <125000000>;
59 	phy-handle = <&rgmii_phy0>;
60 	phy-mode = "rgmii";
61 	pinctrl-names = "default";
62 	pinctrl-0 = <&gmac0_miim
67 	snps,reset-gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_LOW>;
68 	snps,reset-active-low;
69 	/* Reset time is 15ms, 50ms for rtl8211f */
70 	snps,reset-delays-us = <0 15000 50000>;
77 	rgmii_phy0: ethernet-phy@1 {
78 		compatible = "ethernet-phy-ieee802.3-c22";
80 		pinctrl-0 = <&eth_phy0_reset_pin>;
81 		pinctrl-names = "default";
86 	num-lanes = <1>;
87 	reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>;
92 	data-lanes = <1 2>;
97 	num-lanes = <1>;
98 	reset-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
99 	vpcie3v3-supply = <&vcc3v3_pcie>;
104 	num-lanes = <1>;
105 	num-ib-windows = <8>;
106 	num-ob-windows = <8>;
107 	reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
108 	vpcie3v3-supply = <&vcc3v3_pcie>;
114 		eth_phy0_reset_pin: eth-phy0-reset-pin {
119 	gpio-leds {
120 		lan1_led_pin: lan1-led-pin {
124 		lan2_led_pin: lan2-led-pin {
128 		power_led_pin: power-led-pin {
132 		wan_led_pin: wan-led-pin {