Lines Matching +full:cru +full:- +full:bus
1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
3 #include "rk3568-fastrhino-r66s.dtsi"
7 compatible = "lunzn,fastrhino-r68s", "rockchip,rk3568";
15 adc-keys {
16 compatible = "adc-keys";
17 io-channels = <&saradc 0>;
18 io-channel-names = "buttons";
19 keyup-threshold-microvolt = <1800000>;
21 button-recovery {
24 press-threshold-microvolt = <1750>;
30 assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
31 assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>;
32 assigned-clock-rates = <0>, <125000000>;
34 phy-handle = <&rgmii_phy0>;
35 phy-mode = "rgmii-id";
36 pinctrl-names = "default";
37 pinctrl-0 = <&gmac0_miim
46 assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
47 assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>;
48 assigned-clock-rates = <0>, <125000000>;
50 phy-handle = <&rgmii_phy1>;
51 phy-mode = "rgmii-id";
52 pinctrl-names = "default";
53 pinctrl-0 = <&gmac1m1_miim
62 rgmii_phy0: ethernet-phy@1 {
63 compatible = "ethernet-phy-ieee802.3-c22";
65 pinctrl-0 = <ð_phy0_reset_pin>;
66 pinctrl-names = "default";
67 reset-assert-us = <20000>;
68 reset-deassert-us = <100000>;
69 reset-gpios = <&gpio1 RK_PB0 GPIO_ACTIVE_LOW>;
74 rgmii_phy1: ethernet-phy@1 {
75 compatible = "ethernet-phy-ieee802.3-c22";
77 pinctrl-0 = <ð_phy1_reset_pin>;
78 pinctrl-names = "default";
79 reset-assert-us = <20000>;
80 reset-deassert-us = <100000>;
81 reset-gpios = <&gpio1 RK_PB1 GPIO_ACTIVE_LOW>;
87 eth_phy0_reset_pin: eth-phy0-reset-pin {
93 eth_phy1_reset_pin: eth-phy1-reset-pin {
100 vccio3-supply = <&vcc_3v3>;
104 bus-width = <8>;
105 max-frequency = <200000000>;
106 non-removable;
107 pinctrl-names = "default";
108 pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;