Lines Matching full:cru
6 #include <dt-bindings/clock/rk3399-cru.h>
85 clocks = <&cru ARMCLKL>;
104 clocks = <&cru ARMCLKL>;
123 clocks = <&cru ARMCLKL>;
142 clocks = <&cru ARMCLKL>;
161 clocks = <&cru ARMCLKB>;
186 clocks = <&cru ARMCLKB>;
255 clocks = <&cru SCLK_DDRC>;
302 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
303 <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
323 resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
324 <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>,
325 <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>,
326 <&cru SRST_A_PCIE>;
343 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
344 <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
349 resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
350 <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>,
351 <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>,
352 <&cru SRST_A_PCIE>;
370 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
371 <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
372 <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
373 <&cru PCLK_GMAC>;
379 resets = <&cru SRST_A_GMAC>;
392 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
393 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
397 resets = <&cru SRST_SDIO0>;
408 assigned-clocks = <&cru HCLK_SD>;
410 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
411 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
415 resets = <&cru SRST_SDMMC>;
425 assigned-clocks = <&cru SCLK_EMMC>;
427 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
442 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
453 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
464 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
475 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
485 clocks = <&cru PCLK_COREDBG_L>;
493 clocks = <&cru PCLK_COREDBG_L>;
501 clocks = <&cru PCLK_COREDBG_L>;
509 clocks = <&cru PCLK_COREDBG_L>;
517 clocks = <&cru PCLK_COREDBG_B>;
525 clocks = <&cru PCLK_COREDBG_B>;
535 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
536 <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
537 <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
541 resets = <&cru SRST_A_USB3_OTG0>;
549 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru ACLK_USB3OTG0>,
550 <&cru SCLK_USB3OTG0_SUSPEND>;
571 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>,
572 <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
573 <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
577 resets = <&cru SRST_A_USB3_OTG1>;
585 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru ACLK_USB3OTG1>,
586 <&cru SCLK_USB3OTG1_SUSPEND>;
606 assigned-clocks = <&cru SCLK_DP_CORE>, <&cru SCLK_SPDIF_REC_DPTX>;
608 clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>,
609 <&cru SCLK_SPDIF_REC_DPTX>, <&cru PCLK_VIO_GRF>;
613 resets = <&cru SRST_DPTX_SPDIF_REC>, <&cru SRST_P_UPHY0_DPTX>,
614 <&cru SRST_P_UPHY0_APB>, <&cru SRST_DP_CORE>;
675 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
677 resets = <&cru SRST_P_SARADC>;
686 clocks = <&cru HCLK_M_CRYPTO0>, <&cru HCLK_S_CRYPTO0>, <&cru SCLK_CRYPTO0>;
688 resets = <&cru SRST_CRYPTO0>, <&cru SRST_CRYPTO0_S>, <&cru SRST_CRYPTO0_M>;
696 clocks = <&cru HCLK_M_CRYPTO1>, <&cru HCLK_S_CRYPTO1>, <&cru SCLK_CRYPTO1>;
698 resets = <&cru SRST_CRYPTO1>, <&cru SRST_CRYPTO1_S>, <&cru SRST_CRYPTO1_M>;
705 assigned-clocks = <&cru SCLK_I2C1>;
707 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
720 assigned-clocks = <&cru SCLK_I2C2>;
722 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
735 assigned-clocks = <&cru SCLK_I2C3>;
737 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
750 assigned-clocks = <&cru SCLK_I2C5>;
752 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;
765 assigned-clocks = <&cru SCLK_I2C6>;
767 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>;
780 assigned-clocks = <&cru SCLK_I2C7>;
782 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>;
795 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
808 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
821 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
834 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
847 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
862 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
877 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
892 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
907 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
998 assigned-clocks = <&cru SCLK_TSADC>;
1000 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
1002 resets = <&cru SRST_TSADC>;
1159 clocks = <&cru ACLK_IEP>,
1160 <&cru HCLK_IEP>;
1166 clocks = <&cru ACLK_RGA>,
1167 <&cru HCLK_RGA>;
1174 clocks = <&cru ACLK_VCODEC>,
1175 <&cru HCLK_VCODEC>;
1181 clocks = <&cru ACLK_VDU>,
1182 <&cru HCLK_VDU>,
1183 <&cru SCLK_VDU_CA>,
1184 <&cru SCLK_VDU_CORE>;
1193 clocks = <&cru ACLK_GPU>;
1201 clocks = <&cru PCLK_EDP_CTRL>;
1206 clocks = <&cru ACLK_EMMC>;
1212 clocks = <&cru ACLK_GMAC>,
1213 <&cru PCLK_GMAC>;
1219 clocks = <&cru HCLK_SDMMC>,
1220 <&cru SCLK_SDMMC>;
1226 clocks = <&cru HCLK_SDIO>;
1232 clocks = <&cru SCLK_UPHY0_TCPDCORE>,
1233 <&cru SCLK_UPHY0_TCPDPHY_REF>;
1238 clocks = <&cru SCLK_UPHY1_TCPDCORE>,
1239 <&cru SCLK_UPHY1_TCPDPHY_REF>;
1244 clocks = <&cru ACLK_USB3>;
1257 clocks = <&cru ACLK_HDCP>,
1258 <&cru HCLK_HDCP>,
1259 <&cru PCLK_HDCP>;
1265 clocks = <&cru ACLK_ISP0>,
1266 <&cru HCLK_ISP0>;
1273 clocks = <&cru ACLK_ISP1>,
1274 <&cru HCLK_ISP1>;
1287 clocks = <&cru ACLK_VOP0>,
1288 <&cru HCLK_VOP0>;
1295 clocks = <&cru ACLK_VOP1>,
1296 <&cru HCLK_VOP1>;
1431 clocks = <&cru PCLK_DDR_MON>;
1441 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1451 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1461 clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>,
1462 <&cru SCLK_VDU_CA>, <&cru SCLK_VDU_CORE>;
1472 clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>;
1482 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
1492 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>;
1494 resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>;
1504 clocks = <&cru PCLK_EFUSE1024NS>;
1538 clocks = <&cru ACLK_DMAC0_PERILP>;
1549 clocks = <&cru ACLK_DMAC1_PERILP>;
1565 cru: clock-controller@ff760000 { label
1566 compatible = "rockchip,rk3399-cru";
1574 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
1575 <&cru PLL_NPLL>,
1576 <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
1577 <&cru PCLK_PERIHP>,
1578 <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
1579 <&cru PCLK_PERILP0>, <&cru ACLK_CCI>,
1580 <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>,
1581 <&cru ACLK_VIO>, <&cru ACLK_HDCP>,
1582 <&cru ACLK_GIC_PRE>,
1583 <&cru PCLK_DDR>,
1584 <&cru ACLK_VDU>;
1612 clocks = <&cru SCLK_MIPIDPHY_REF>,
1613 <&cru SCLK_DPHY_RX0_CFG>,
1614 <&cru PCLK_VIO_GRF>;
1624 clocks = <&cru SCLK_USB2PHY0_REF>;
1651 clocks = <&cru SCLK_USB2PHY1_REF>;
1687 clocks = <&cru SCLK_PCIEPHY_REF>;
1690 resets = <&cru SRST_PCIEPHY>;
1699 clocks = <&cru SCLK_UPHY0_TCPDCORE>,
1700 <&cru SCLK_UPHY0_TCPDPHY_REF>;
1702 assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>;
1705 resets = <&cru SRST_UPHY0>,
1706 <&cru SRST_UPHY0_PIPE_L00>,
1707 <&cru SRST_P_UPHY0_TCPHY>;
1724 clocks = <&cru SCLK_UPHY1_TCPDCORE>,
1725 <&cru SCLK_UPHY1_TCPDPHY_REF>;
1727 assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>;
1730 resets = <&cru SRST_UPHY1>,
1731 <&cru SRST_UPHY1_PIPE_L00>,
1732 <&cru SRST_P_UPHY1_TCPHY>;
1749 clocks = <&cru PCLK_WDT>;
1757 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>;
1768 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
1784 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
1800 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
1815 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
1825 assigned-clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
1827 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1831 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>;
1870 clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
1881 assigned-clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
1883 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
1887 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;
1926 clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
1937 clocks = <&cru SCLK_ISP0>,
1938 <&cru ACLK_ISP0_WRAPPER>,
1939 <&cru HCLK_ISP0_WRAPPER>;
1963 clocks = <&cru ACLK_ISP0_WRAPPER>, <&cru HCLK_ISP0_WRAPPER>;
1974 clocks = <&cru SCLK_ISP1>,
1975 <&cru ACLK_ISP1_WRAPPER>,
1976 <&cru HCLK_ISP1_WRAPPER>;
2000 clocks = <&cru ACLK_ISP1_WRAPPER>, <&cru HCLK_ISP1_WRAPPER>;
2027 clocks = <&cru PCLK_HDMI_CTRL>,
2028 <&cru SCLK_HDMI_SFR>,
2029 <&cru SCLK_HDMI_CEC>,
2030 <&cru PCLK_VIO_GRF>,
2031 <&cru PLL_VPLL>;
2067 clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI0>,
2068 <&cru SCLK_DPHY_TX0_CFG>, <&cru PCLK_VIO_GRF>;
2071 resets = <&cru SRST_P_MIPI_DSI0>;
2108 clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI1>,
2109 <&cru SCLK_DPHY_TX1RX1_CFG>, <&cru PCLK_VIO_GRF>;
2112 resets = <&cru SRST_P_MIPI_DSI1>;
2150 clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>, <&cru PCLK_VIO_GRF>;
2155 resets = <&cru SRST_P_EDP_CTRL>;
2193 clocks = <&cru ACLK_GPU>;
2237 clocks = <&cru PCLK_GPIO2>;
2250 clocks = <&cru PCLK_GPIO3>;
2263 clocks = <&cru PCLK_GPIO4>;