Lines Matching full:cru
6 #include <dt-bindings/clock/rk3328-cru.h>
44 clocks = <&cru ARMCLK>;
63 clocks = <&cru ARMCLK>;
82 clocks = <&cru ARMCLK>;
101 clocks = <&cru ARMCLK>;
246 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
258 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
270 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>;
282 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>;
295 clocks = <&cru SCLK_PDM>, <&cru HCLK_PDM>;
340 clocks = <&cru ACLK_RKVDEC>,
341 <&cru HCLK_RKVDEC>,
342 <&cru SCLK_VDEC_CABAC>,
343 <&cru SCLK_VDEC_CORE>;
348 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
367 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
382 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
397 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
414 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>;
427 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
440 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
453 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
466 clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>;
479 clocks = <&cru PCLK_WDT>;
485 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
496 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
507 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
518 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
532 clocks = <&cru ACLK_DMAC>;
581 assigned-clocks = <&cru SCLK_TSADC>;
583 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
589 resets = <&cru SRST_TSADC>;
602 clocks = <&cru SCLK_EFUSE>;
627 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
629 resets = <&cru SRST_SARADC_P>;
651 clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>;
653 resets = <&cru SRST_GPU_A>;
660 clocks = <&cru ACLK_H265>, <&cru PCLK_H265>;
670 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
681 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
691 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
701 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>,
702 <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>;
704 assigned-clocks = <&cru ACLK_RKVDEC>, <&cru SCLK_VDEC_CABAC>,
705 <&cru SCLK_VDEC_CORE>;
715 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>;
725 clocks = <&cru ACLK_VOP>, <&cru DCLK_LCDC>, <&cru HCLK_VOP>;
727 resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>;
747 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
758 clocks = <&cru PCLK_HDMI>,
759 <&cru SCLK_HDMI_SFC>,
760 <&cru SCLK_RTC32K>;
793 clocks = <&cru PCLK_ACODECPHY>, <&cru SCLK_I2S1>;
804 clocks = <&cru PCLK_HDMIPHY>, <&xin24m>, <&cru DCLK_HDMIPHY>;
814 cru: clock-controller@ff440000 { label
815 compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon";
827 <&cru DCLK_LCDC>, <&cru SCLK_PDM>,
828 <&cru SCLK_RTC32K>, <&cru SCLK_UART0>,
829 <&cru SCLK_UART1>, <&cru SCLK_UART2>,
830 <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
831 <&cru ACLK_VIO_PRE>, <&cru ACLK_RGA_PRE>,
832 <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>,
833 <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>,
834 <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>,
835 <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>,
836 <&cru SCLK_SDIO>, <&cru SCLK_TSP>,
837 <&cru SCLK_WIFI>, <&cru ARMCLK>,
838 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
839 <&cru ACLK_BUS_PRE>, <&cru HCLK_BUS_PRE>,
840 <&cru PCLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
841 <&cru HCLK_PERI>, <&cru PCLK_PERI>,
842 <&cru SCLK_RTC32K>;
844 <&cru HDMIPHY>, <&cru PLL_APLL>,
845 <&cru PLL_GPLL>, <&xin24m>,
880 assigned-clocks = <&cru USB480M>;
907 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
908 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
912 resets = <&cru SRST_MMC0>;
921 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
922 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
926 resets = <&cru SRST_SDIO>;
935 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
936 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
940 resets = <&cru SRST_EMMC>;
950 clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_RX>,
951 <&cru SCLK_MAC2IO_TX>, <&cru SCLK_MAC2IO_REF>,
952 <&cru SCLK_MAC2IO_REFOUT>, <&cru ACLK_MAC2IO>,
953 <&cru PCLK_MAC2IO>;
958 resets = <&cru SRST_GMAC2IO_A>;
973 clocks = <&cru SCLK_MAC2PHY_SRC>, <&cru SCLK_MAC2PHY_RXTX>,
974 <&cru SCLK_MAC2PHY_RXTX>, <&cru SCLK_MAC2PHY_REF>,
975 <&cru ACLK_MAC2PHY>, <&cru PCLK_MAC2PHY>,
976 <&cru SCLK_MAC2PHY_OUT>;
981 resets = <&cru SRST_GMAC2PHY_A>;
999 clocks = <&cru SCLK_MAC2PHY_OUT>;
1000 resets = <&cru SRST_MACPHY>;
1013 clocks = <&cru HCLK_OTG>;
1028 clocks = <&cru HCLK_HOST0>, <&u2phy>;
1038 clocks = <&cru HCLK_HOST0>, <&u2phy>;
1048 clocks = <&cru HCLK_SDMMC_EXT>, <&cru SCLK_SDMMC_EXT>,
1049 <&cru SCLK_SDMMC_EXT_DRV>, <&cru SCLK_SDMMC_EXT_SAMPLE>;
1053 resets = <&cru SRST_SDMMCEXT>;
1062 clocks = <&cru SCLK_USB3OTG_REF>, <&cru SCLK_USB3OTG_SUSPEND>,
1063 <&cru ACLK_USB3OTG>;
1094 clocks = <&cru HCLK_CRYPTO_MST>, <&cru HCLK_CRYPTO_SLV>,
1095 <&cru SCLK_CRYPTO>;
1097 resets = <&cru SRST_CRYPTO>;
1112 clocks = <&cru PCLK_GPIO0>;
1125 clocks = <&cru PCLK_GPIO1>;
1138 clocks = <&cru PCLK_GPIO2>;
1151 clocks = <&cru PCLK_GPIO3>;