Lines Matching full:cru
7 #include <dt-bindings/clock/rk3308-cru.h>
51 clocks = <&cru ARMCLK>;
201 assigned-clocks = <&cru USB480M>;
203 clocks = <&cru SCLK_USBPHY_REF>;
245 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>;
258 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
271 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
284 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
297 clocks = <&cru PCLK_WDT>;
306 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
319 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
332 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
345 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
358 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
373 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
388 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
403 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
415 clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>;
426 clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>;
437 clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>;
448 clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>;
459 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
470 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
481 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
492 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
503 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
514 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
525 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
536 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
548 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER0>;
556 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
559 resets = <&cru SRST_SARADC_P>;
569 clocks = <&cru SCLK_OTP_USR>, <&cru PCLK_OTP_NS>,
570 <&cru PCLK_OTP_PHY>;
572 resets = <&cru SRST_OTP_PHY>;
594 clocks = <&cru ACLK_DMAC0>;
605 clocks = <&cru ACLK_DMAC1>;
620 clocks = <&cru SCLK_I2S2_8CH_TX>,
621 <&cru SCLK_I2S2_8CH_RX>,
622 <&cru HCLK_I2S2_8CH>;
625 resets = <&cru SRST_I2S2_8CH_TX_M>, <&cru SRST_I2S2_8CH_RX_M>;
641 clocks = <&cru SCLK_I2S3_8CH_TX>,
642 <&cru SCLK_I2S3_8CH_RX>,
643 <&cru HCLK_I2S3_8CH>;
646 resets = <&cru SRST_I2S3_8CH_TX_M>, <&cru SRST_I2S3_8CH_RX_M>;
656 clocks = <&cru SCLK_I2S0_2CH>, <&cru HCLK_I2S0_2CH>;
660 resets = <&cru SRST_I2S0_2CH_M>, <&cru SRST_I2S0_2CH_H>;
674 clocks = <&cru SCLK_I2S1_2CH>, <&cru HCLK_I2S1_2CH>;
678 resets = <&cru SRST_I2S1_2CH_M>, <&cru SRST_I2S1_2CH_H>;
687 clocks = <&cru SCLK_SPDIF_TX>, <&cru HCLK_SPDIFTX>;
701 clocks = <&cru HCLK_OTG>;
716 clocks = <&cru HCLK_HOST>, <&cru HCLK_HOST_ARB>, <&u2phy>;
726 clocks = <&cru HCLK_HOST>, <&cru HCLK_HOST_ARB>, <&u2phy>;
737 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
738 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
752 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
753 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
765 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
766 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
780 clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>;
782 assigned-clocks = <&cru SCLK_NANDC>;
795 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX_TX>,
796 <&cru SCLK_MAC_RX_TX>, <&cru SCLK_MAC_REF>,
797 <&cru SCLK_MAC>, <&cru ACLK_MAC>,
798 <&cru PCLK_MAC>, <&cru SCLK_MAC_RMII>;
806 resets = <&cru SRST_MAC_A>;
816 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
823 cru: clock-controller@ff500000 { label
824 compatible = "rockchip,rk3308-cru";
831 assigned-clocks = <&cru SCLK_RTC32K>;
840 clocks = <&cru SCLK_I2S2_8CH_TX_OUT>,
841 <&cru SCLK_I2S2_8CH_RX_OUT>,
842 <&cru PCLK_ACODEC>;
844 resets = <&cru SRST_ACODEC_P>;
890 clocks = <&cru PCLK_GPIO0>;
901 clocks = <&cru PCLK_GPIO1>;
912 clocks = <&cru PCLK_GPIO2>;
923 clocks = <&cru PCLK_GPIO3>;
934 clocks = <&cru PCLK_GPIO4>;