dts/rockchip/px30-engicam-common.dtsi

1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
15 	vcc5v0_sys: vcc5v0-sys {
16 		compatible = "regulator-fixed";
17 		regulator-name = "vcc5v0_sys";	/* +5V */
18 		regulator-always-on;
19 		regulator-boot-on;
20 		regulator-min-microvolt = <5000000>;
21 		regulator-max-microvolt = <5000000>;
24 	sdio_pwrseq: sdio-pwrseq {
25 		compatible = "mmc-pwrseq-simple";
27 		clock-names = "ext_clock";
28 		post-power-on-delay-ms = <80>;
29 		pinctrl-names = "default";
30 		pinctrl-0 = <&wifi_enable_h>;
33 	vcc3v3_btreg: vcc3v3-btreg {
34 		compatible = "regulator-gpio";
35 		enable-active-high;
36 		pinctrl-names = "default";
37 		pinctrl-0 = <&bt_enable_h>;
38 		regulator-name = "btreg-gpio-supply";
39 		regulator-min-microvolt = <3300000>;
40 		regulator-max-microvolt = <3300000>;
41 		regulator-always-on;
45 	vcc3v3_rf_aux_mod: vcc3v3-rf-aux-mod {
46 		compatible = "regulator-fixed";
47 		regulator-name = "vcc3v3_rf_aux_mod";
48 		regulator-min-microvolt = <3300000>;
49 		regulator-max-microvolt = <3300000>;
50 		regulator-always-on;
51 		regulator-boot-on;
52 		vin-supply = <&vcc5v0_sys>;
56 		compatible = "fixed-clock";
57 		#clock-cells = <0>;
58 		clock-frequency = <32768>;
59 		clock-output-names = "xin32k";
64 	#address-cells = <1>;
65 	#size-cells = <0>;
66 	bus-width = <4>;
67 	clock-frequency = <50000000>;
68 	cap-sdio-irq;
69 	cap-sd-highspeed;
70 	keep-power-in-suspend;
71 	mmc-pwrseq = <&sdio_pwrseq>;
72 	non-removable;
73 	sd-uhs-sdr104;
77 		compatible = "brcm,bcm4329-fmac";
84 	phy-supply = <&vcc_3v3>;	/* +3V3_SOM */
85 	snps,reset-active-low;
86 	snps,reset-delays-us = <0 50000 50000>;
87 	snps,reset-gpio = <&gpio2 RK_PB5 GPIO_ACTIVE_HIGH>;
96 	cap-sd-highspeed;
97 	card-detect-delay = <800>;
98 	vmmc-supply = <&vcc_3v3>;	/* +3V3_SOM */
99 	vqmmc-supply = <&vcc_3v3>;
106 	u2phy_host: host-port {
110 	u2phy_otg: otg-port {
116 	pinctrl-0 = <&uart2m1_xfer>;