Lines Matching +full:- +full:resets
1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 #include <dt-bindings/clock/renesas,r9a09g057-cpg.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #address-cells = <2>;
14 #size-cells = <2>;
16 audio_extal_clk: audio-clk {
17 compatible = "fixed-clock";
18 #clock-cells = <0>;
20 clock-frequency = <0>;
24 #address-cells = <1>;
25 #size-cells = <0>;
28 compatible = "arm,cortex-a55";
31 next-level-cache = <&L3_CA55>;
32 enable-method = "psci";
36 compatible = "arm,cortex-a55";
39 next-level-cache = <&L3_CA55>;
40 enable-method = "psci";
44 compatible = "arm,cortex-a55";
47 next-level-cache = <&L3_CA55>;
48 enable-method = "psci";
52 compatible = "arm,cortex-a55";
55 next-level-cache = <&L3_CA55>;
56 enable-method = "psci";
59 L3_CA55: cache-controller-0 {
61 cache-unified;
62 cache-size = <0x100000>;
63 cache-level = <3>;
68 compatible = "arm,psci-1.0", "arm,psci-0.2";
72 qextal_clk: qextal-clk {
73 compatible = "fixed-clock";
74 #clock-cells = <0>;
76 clock-frequency = <0>;
79 rtxin_clk: rtxin-clk {
80 compatible = "fixed-clock";
81 #clock-cells = <0>;
83 clock-frequency = <0>;
87 compatible = "simple-bus";
88 interrupt-parent = <&gic>;
89 #address-cells = <2>;
90 #size-cells = <2>;
94 compatible = "renesas,r9a09g057-pinctrl";
97 gpio-controller;
98 #gpio-cells = <2>;
99 gpio-ranges = <&pinctrl 0 0 96>;
100 #interrupt-cells = <2>;
101 interrupt-controller;
102 power-domains = <&cpg>;
103 resets = <&cpg 0xa5>, <&cpg 0xa6>;
106 cpg: clock-controller@10420000 {
107 compatible = "renesas,r9a09g057-cpg";
110 clock-names = "audio_extal", "rtxin", "qextal";
111 #clock-cells = <2>;
112 #reset-cells = <1>;
113 #power-domain-cells = <0>;
116 sys: system-controller@10430000 {
117 compatible = "renesas,r9a09g057-sys";
120 resets = <&cpg 0x30>;
125 compatible = "renesas,r9a09g057-ostm", "renesas,ostm";
129 resets = <&cpg 0x6d>;
130 power-domains = <&cpg>;
135 compatible = "renesas,r9a09g057-ostm", "renesas,ostm";
139 resets = <&cpg 0x6e>;
140 power-domains = <&cpg>;
145 compatible = "renesas,r9a09g057-ostm", "renesas,ostm";
149 resets = <&cpg 0x6f>;
150 power-domains = <&cpg>;
155 compatible = "renesas,r9a09g057-ostm", "renesas,ostm";
159 resets = <&cpg 0x70>;
160 power-domains = <&cpg>;
165 compatible = "renesas,r9a09g057-ostm", "renesas,ostm";
169 resets = <&cpg 0x71>;
170 power-domains = <&cpg>;
175 compatible = "renesas,r9a09g057-ostm", "renesas,ostm";
179 resets = <&cpg 0x72>;
180 power-domains = <&cpg>;
185 compatible = "renesas,r9a09g057-ostm", "renesas,ostm";
189 resets = <&cpg 0x73>;
190 power-domains = <&cpg>;
195 compatible = "renesas,r9a09g057-ostm", "renesas,ostm";
199 resets = <&cpg 0x74>;
200 power-domains = <&cpg>;
205 compatible = "renesas,r9a09g057-wdt";
208 clock-names = "pclk", "oscclk";
209 resets = <&cpg 0x75>;
210 power-domains = <&cpg>;
215 compatible = "renesas,r9a09g057-wdt";
218 clock-names = "pclk", "oscclk";
219 resets = <&cpg 0x76>;
220 power-domains = <&cpg>;
225 compatible = "renesas,r9a09g057-wdt";
228 clock-names = "pclk", "oscclk";
229 resets = <&cpg 0x77>;
230 power-domains = <&cpg>;
235 compatible = "renesas,r9a09g057-wdt";
238 clock-names = "pclk", "oscclk";
239 resets = <&cpg 0x78>;
240 power-domains = <&cpg>;
245 compatible = "renesas,scif-r9a09g057";
256 interrupt-names = "eri", "rxi", "txi", "bri", "dri",
257 "tei", "tei-dri", "rxi-edge", "txi-edge";
259 clock-names = "fck";
260 power-domains = <&cpg>;
261 resets = <&cpg 0x95>;
266 compatible = "renesas,riic-r9a09g057";
276 interrupt-names = "tei", "ri", "ti", "spi", "sti",
279 resets = <&cpg 0x98>;
280 power-domains = <&cpg>;
281 #address-cells = <1>;
282 #size-cells = <0>;
287 compatible = "renesas,riic-r9a09g057";
297 interrupt-names = "tei", "ri", "ti", "spi", "sti",
300 resets = <&cpg 0x99>;
301 power-domains = <&cpg>;
302 #address-cells = <1>;
303 #size-cells = <0>;
308 compatible = "renesas,riic-r9a09g057";
318 interrupt-names = "tei", "ri", "ti", "spi", "sti",
321 resets = <&cpg 0x9a>;
322 power-domains = <&cpg>;
323 #address-cells = <1>;
324 #size-cells = <0>;
329 compatible = "renesas,riic-r9a09g057";
339 interrupt-names = "tei", "ri", "ti", "spi", "sti",
342 resets = <&cpg 0x9b>;
343 power-domains = <&cpg>;
344 #address-cells = <1>;
345 #size-cells = <0>;
350 compatible = "renesas,riic-r9a09g057";
360 interrupt-names = "tei", "ri", "ti", "spi", "sti",
363 resets = <&cpg 0x9c>;
364 power-domains = <&cpg>;
365 #address-cells = <1>;
366 #size-cells = <0>;
371 compatible = "renesas,riic-r9a09g057";
381 interrupt-names = "tei", "ri", "ti", "spi", "sti",
384 resets = <&cpg 0x9d>;
385 power-domains = <&cpg>;
386 #address-cells = <1>;
387 #size-cells = <0>;
392 compatible = "renesas,riic-r9a09g057";
402 interrupt-names = "tei", "ri", "ti", "spi", "sti",
405 resets = <&cpg 0x9e>;
406 power-domains = <&cpg>;
407 #address-cells = <1>;
408 #size-cells = <0>;
413 compatible = "renesas,riic-r9a09g057";
423 interrupt-names = "tei", "ri", "ti", "spi", "sti",
426 resets = <&cpg 0x9f>;
427 power-domains = <&cpg>;
428 #address-cells = <1>;
429 #size-cells = <0>;
434 compatible = "renesas,riic-r9a09g057";
444 interrupt-names = "tei", "ri", "ti", "spi", "sti",
447 resets = <&cpg 0xa0>;
448 power-domains = <&cpg>;
449 #address-cells = <1>;
450 #size-cells = <0>;
454 gic: interrupt-controller@14900000 {
455 compatible = "arm,gic-v3";
458 #interrupt-cells = <3>;
459 #address-cells = <0>;
460 interrupt-controller;
465 compatible = "renesas,sdhi-r9a09g057";
471 clock-names = "core", "clkh", "cd", "aclk";
472 resets = <&cpg 0xa7>;
473 power-domains = <&cpg>;
478 compatible = "renesas,sdhi-r9a09g057";
484 clock-names = "core", "clkh", "cd", "aclk";
485 resets = <&cpg 0xa8>;
486 power-domains = <&cpg>;
491 compatible = "renesas,sdhi-r9a09g057";
497 clock-names = "core", "clkh", "cd", "aclk";
498 resets = <&cpg 0xa9>;
499 power-domains = <&cpg>;
505 compatible = "arm,armv8-timer";
506 interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
511 interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt";