dts/renesas/r9a09g011.dtsi

9 #include <dt-bindings/clock/r9a09g011-cpg.h>
41 			clocks = <&cpg CPG_MOD R9A09G011_CA53_CLK>;
68 			clocks = <&cpg CPG_MOD R9A09G011_GIC_CLK>;
78 			clocks = <&cpg CPG_MOD R9A09G011_SDI0_IMCLK>,
79 				 <&cpg CPG_MOD R9A09G011_SDI0_CLK_HS>,
80 				 <&cpg CPG_MOD R9A09G011_SDI0_IMCLK2>,
81 				 <&cpg CPG_MOD R9A09G011_SDI0_ACLK>;
83 			resets = <&cpg R9A09G011_SDI0_IXRST>;
84 			power-domains = <&cpg>;
94 			clocks = <&cpg CPG_MOD R9A09G011_SDI1_IMCLK>,
95 				 <&cpg CPG_MOD R9A09G011_SDI1_CLK_HS>,
96 				 <&cpg CPG_MOD R9A09G011_SDI1_IMCLK2>,
97 				 <&cpg CPG_MOD R9A09G011_SDI1_ACLK>;
99 			resets = <&cpg R9A09G011_SDI1_IXRST>;
100 			power-domains = <&cpg>;
110 			clocks = <&cpg CPG_MOD R9A09G011_EMM_IMCLK>,
111 				 <&cpg CPG_MOD R9A09G011_EMM_CLK_HS>,
112 				 <&cpg CPG_MOD R9A09G011_EMM_IMCLK2>,
113 				 <&cpg CPG_MOD R9A09G011_EMM_ACLK>;
115 			resets = <&cpg R9A09G011_EMM_IXRST>;
116 			power-domains = <&cpg>;
128 			clocks = <&cpg CPG_MOD R9A09G011_USB_ACLK_P>,
129 				 <&cpg CPG_MOD R9A09G011_USB_PCLK>;
131 			resets = <&cpg R9A09G011_USB_DRD_RESET>;
132 			power-domains = <&cpg>;
143 				clocks = <&cpg CPG_MOD R9A09G011_USB_ACLK_H>,
144 					 <&cpg CPG_MOD R9A09G011_USB_PCLK>;
146 				resets = <&cpg R9A09G011_USB_ARESETN_H>;
147 				power-domains = <&cpg>;
156 				clocks = <&cpg CPG_MOD R9A09G011_USB_ACLK_P>,
157 					 <&cpg CPG_MOD R9A09G011_USB_PCLK>;
159 				resets = <&cpg R9A09G011_USB_ARESETN_P>;
160 				power-domains = <&cpg>;
205 			clocks = <&cpg CPG_MOD R9A09G011_ETH0_CLK_AXI>,
206 				 <&cpg CPG_MOD R9A09G011_ETH0_CLK_CHI>,
207 				 <&cpg CPG_MOD R9A09G011_ETH0_GPTP_EXT>;
209 			resets = <&cpg R9A09G011_ETH0_RST_HW_N>;
210 			power-domains = <&cpg>;
216 		cpg: clock-controller@a3500000 {  label
217 			compatible = "renesas,r9a09g011-cpg";
243 			clocks = <&cpg CPG_MOD R9A09G011_CSI0_CLK>,
244 				 <&cpg CPG_MOD R9A09G011_CPERI_GRPG_PCLK>;
246 			resets = <&cpg R9A09G011_CSI_GPG_PRESETN>;
247 			power-domains = <&cpg>;
257 			clocks = <&cpg CPG_MOD R9A09G011_CSI4_CLK>,
258 				 <&cpg CPG_MOD R9A09G011_CPERI_GRPH_PCLK>;
260 			resets = <&cpg R9A09G011_CSI_GPH_PRESETN>;
261 			power-domains = <&cpg>;
275 			clocks = <&cpg CPG_MOD R9A09G011_IIC_PCLK0>;
276 			resets = <&cpg R9A09G011_IIC_GPA_PRESETN>;
277 			power-domains = <&cpg>;
289 			clocks = <&cpg CPG_MOD R9A09G011_IIC_PCLK1>;
290 			resets = <&cpg R9A09G011_IIC_GPB_PRESETN>;
291 			power-domains = <&cpg>;
299 			clocks = <&cpg CPG_MOD R9A09G011_URT0_CLK>,
300 				 <&cpg CPG_MOD R9A09G011_URT_PCLK>;
309 			clocks = <&cpg CPG_MOD R9A09G011_WDT0_PCLK>,
310 				 <&cpg CPG_MOD R9A09G011_WDT0_CLK>;
313 			resets = <&cpg R9A09G011_WDT0_PRESETN>;
314 			power-domains = <&cpg>;
363 			clocks = <&cpg CPG_MOD R9A09G011_PFC_PCLK>;
364 			power-domains = <&cpg>;
365 			resets = <&cpg R9A09G011_PFC_PRESETN>;