Lines Matching full:cpg
9 #include <dt-bindings/clock/r9a08g045-cpg.h>
27 clocks = <&cpg CPG_CORE R9A08G045_CLK_I>;
68 clocks = <&cpg CPG_MOD R9A08G045_SCIF0_CLK_PCK>;
70 power-domains = <&cpg>;
71 resets = <&cpg R9A08G045_SCIF0_RST_SYSTEM_N>;
88 clocks = <&cpg CPG_MOD R9A08G045_I2C0_PCLK>;
90 resets = <&cpg R9A08G045_I2C0_MRST>;
91 power-domains = <&cpg>;
110 clocks = <&cpg CPG_MOD R9A08G045_I2C1_PCLK>;
112 resets = <&cpg R9A08G045_I2C1_MRST>;
113 power-domains = <&cpg>;
132 clocks = <&cpg CPG_MOD R9A08G045_I2C2_PCLK>;
134 resets = <&cpg R9A08G045_I2C2_MRST>;
135 power-domains = <&cpg>;
154 clocks = <&cpg CPG_MOD R9A08G045_I2C3_PCLK>;
156 resets = <&cpg R9A08G045_I2C3_MRST>;
157 power-domains = <&cpg>;
163 cpg: clock-controller@11010000 { label
164 compatible = "renesas,r9a08g045-cpg";
194 clocks = <&cpg CPG_MOD R9A08G045_GPIO_HCLK>;
195 power-domains = <&cpg>;
196 resets = <&cpg R9A08G045_GPIO_RSTN>,
197 <&cpg R9A08G045_GPIO_PORT_RESETN>,
198 <&cpg R9A08G045_GPIO_SPARE_RESETN>;
265 clocks = <&cpg CPG_MOD R9A08G045_IA55_CLK>,
266 <&cpg CPG_MOD R9A08G045_IA55_PCLK>;
268 power-domains = <&cpg>;
269 resets = <&cpg R9A08G045_IA55_RESETN>;
299 clocks = <&cpg CPG_MOD R9A08G045_DMAC_ACLK>,
300 <&cpg CPG_MOD R9A08G045_DMAC_PCLK>;
302 power-domains = <&cpg>;
303 resets = <&cpg R9A08G045_DMAC_ARESETN>,
304 <&cpg R9A08G045_DMAC_RST_ASYNC>;
315 clocks = <&cpg CPG_MOD R9A08G045_SDHI0_IMCLK>,
316 <&cpg CPG_MOD R9A08G045_SDHI0_CLK_HS>,
317 <&cpg CPG_MOD R9A08G045_SDHI0_IMCLK2>,
318 <&cpg CPG_MOD R9A08G045_SDHI0_ACLK>;
320 resets = <&cpg R9A08G045_SDHI0_IXRST>;
321 power-domains = <&cpg>;
330 clocks = <&cpg CPG_MOD R9A08G045_SDHI1_IMCLK>,
331 <&cpg CPG_MOD R9A08G045_SDHI1_CLK_HS>,
332 <&cpg CPG_MOD R9A08G045_SDHI1_IMCLK2>,
333 <&cpg CPG_MOD R9A08G045_SDHI1_ACLK>;
335 resets = <&cpg R9A08G045_SDHI1_IXRST>;
336 power-domains = <&cpg>;
345 clocks = <&cpg CPG_MOD R9A08G045_SDHI2_IMCLK>,
346 <&cpg CPG_MOD R9A08G045_SDHI2_CLK_HS>,
347 <&cpg CPG_MOD R9A08G045_SDHI2_IMCLK2>,
348 <&cpg CPG_MOD R9A08G045_SDHI2_ACLK>;
350 resets = <&cpg R9A08G045_SDHI2_IXRST>;
351 power-domains = <&cpg>;
363 clocks = <&cpg CPG_MOD R9A08G045_ETH0_CLK_AXI>,
364 <&cpg CPG_MOD R9A08G045_ETH0_CLK_CHI>,
365 <&cpg CPG_MOD R9A08G045_ETH0_REFCLK>;
367 resets = <&cpg R9A08G045_ETH0_RST_HW_N>;
368 power-domains = <&cpg>;
382 clocks = <&cpg CPG_MOD R9A08G045_ETH1_CLK_AXI>,
383 <&cpg CPG_MOD R9A08G045_ETH1_CLK_CHI>,
384 <&cpg CPG_MOD R9A08G045_ETH1_REFCLK>;
386 resets = <&cpg R9A08G045_ETH1_RST_HW_N>;
387 power-domains = <&cpg>;
406 clocks = <&cpg CPG_MOD R9A08G045_WDT0_PCLK>,
407 <&cpg CPG_MOD R9A08G045_WDT0_CLK>;
412 resets = <&cpg R9A08G045_WDT0_PRESETN>;
413 power-domains = <&cpg>;