Lines Matching full:cpg
9 #include <dt-bindings/clock/r9a07g054-cpg.h>
94 clocks = <&cpg CPG_CORE R9A07G054_CLK_I>;
104 clocks = <&cpg CPG_CORE R9A07G054_CLK_I>;
240 clocks = <&cpg CPG_MOD R9A07G054_MTU_X_MCK_MTU3>;
241 power-domains = <&cpg>;
242 resets = <&cpg R9A07G054_MTU_X_PRESET_MTU3>;
255 clocks = <&cpg CPG_MOD R9A07G054_SSI0_PCLK2>,
256 <&cpg CPG_MOD R9A07G054_SSI0_PCLK_SFR>,
259 resets = <&cpg R9A07G054_SSI0_RST_M2_REG>;
262 power-domains = <&cpg>;
275 clocks = <&cpg CPG_MOD R9A07G054_SSI1_PCLK2>,
276 <&cpg CPG_MOD R9A07G054_SSI1_PCLK_SFR>,
279 resets = <&cpg R9A07G054_SSI1_RST_M2_REG>;
282 power-domains = <&cpg>;
294 clocks = <&cpg CPG_MOD R9A07G054_SSI2_PCLK2>,
295 <&cpg CPG_MOD R9A07G054_SSI2_PCLK_SFR>,
298 resets = <&cpg R9A07G054_SSI2_RST_M2_REG>;
301 power-domains = <&cpg>;
314 clocks = <&cpg CPG_MOD R9A07G054_SSI3_PCLK2>,
315 <&cpg CPG_MOD R9A07G054_SSI3_PCLK_SFR>,
318 resets = <&cpg R9A07G054_SSI3_RST_M2_REG>;
321 power-domains = <&cpg>;
333 clocks = <&cpg CPG_MOD R9A07G054_RSPI0_CLKB>;
334 resets = <&cpg R9A07G054_RSPI0_RST>;
337 power-domains = <&cpg>;
351 clocks = <&cpg CPG_MOD R9A07G054_RSPI1_CLKB>;
352 resets = <&cpg R9A07G054_RSPI1_RST>;
355 power-domains = <&cpg>;
369 clocks = <&cpg CPG_MOD R9A07G054_RSPI2_CLKB>;
370 resets = <&cpg R9A07G054_RSPI2_RST>;
373 power-domains = <&cpg>;
392 clocks = <&cpg CPG_MOD R9A07G054_SCIF0_CLK_PCK>;
394 power-domains = <&cpg>;
395 resets = <&cpg R9A07G054_SCIF0_RST_SYSTEM_N>;
411 clocks = <&cpg CPG_MOD R9A07G054_SCIF1_CLK_PCK>;
413 power-domains = <&cpg>;
414 resets = <&cpg R9A07G054_SCIF1_RST_SYSTEM_N>;
430 clocks = <&cpg CPG_MOD R9A07G054_SCIF2_CLK_PCK>;
432 power-domains = <&cpg>;
433 resets = <&cpg R9A07G054_SCIF2_RST_SYSTEM_N>;
449 clocks = <&cpg CPG_MOD R9A07G054_SCIF3_CLK_PCK>;
451 power-domains = <&cpg>;
452 resets = <&cpg R9A07G054_SCIF3_RST_SYSTEM_N>;
468 clocks = <&cpg CPG_MOD R9A07G054_SCIF4_CLK_PCK>;
470 power-domains = <&cpg>;
471 resets = <&cpg R9A07G054_SCIF4_RST_SYSTEM_N>;
483 clocks = <&cpg CPG_MOD R9A07G054_SCI0_CLKP>;
485 power-domains = <&cpg>;
486 resets = <&cpg R9A07G054_SCI0_RST>;
498 clocks = <&cpg CPG_MOD R9A07G054_SCI1_CLKP>;
500 power-domains = <&cpg>;
501 resets = <&cpg R9A07G054_SCI1_RST>;
519 clocks = <&cpg CPG_MOD R9A07G054_CANFD_PCLK>,
520 <&cpg CPG_CORE R9A07G054_CLK_P0_DIV2>,
523 assigned-clocks = <&cpg CPG_CORE R9A07G054_CLK_P0_DIV2>;
525 resets = <&cpg R9A07G054_CANFD_RSTP_N>,
526 <&cpg R9A07G054_CANFD_RSTC_N>;
528 power-domains = <&cpg>;
554 clocks = <&cpg CPG_MOD R9A07G054_I2C0_PCLK>;
556 resets = <&cpg R9A07G054_I2C0_MRST>;
557 power-domains = <&cpg>;
576 clocks = <&cpg CPG_MOD R9A07G054_I2C1_PCLK>;
578 resets = <&cpg R9A07G054_I2C1_MRST>;
579 power-domains = <&cpg>;
598 clocks = <&cpg CPG_MOD R9A07G054_I2C2_PCLK>;
600 resets = <&cpg R9A07G054_I2C2_MRST>;
601 power-domains = <&cpg>;
620 clocks = <&cpg CPG_MOD R9A07G054_I2C3_PCLK>;
622 resets = <&cpg R9A07G054_I2C3_MRST>;
623 power-domains = <&cpg>;
631 clocks = <&cpg CPG_MOD R9A07G054_ADC_ADCLK>,
632 <&cpg CPG_MOD R9A07G054_ADC_PCLK>;
634 resets = <&cpg R9A07G054_ADC_PRESETN>,
635 <&cpg R9A07G054_ADC_ADRST_N>;
637 power-domains = <&cpg>;
673 clocks = <&cpg CPG_MOD R9A07G054_TSU_PCLK>;
674 resets = <&cpg R9A07G054_TSU_PRESETN>;
675 power-domains = <&cpg>;
687 clocks = <&cpg CPG_MOD R9A07G054_SPI_CLK2>,
688 <&cpg CPG_MOD R9A07G054_SPI_CLK>;
689 resets = <&cpg R9A07G054_SPI_RST>;
690 power-domains = <&cpg>;
699 clocks = <&cpg CPG_MOD R9A07G054_CRU_VCLK>,
700 <&cpg CPG_MOD R9A07G054_CRU_PCLK>,
701 <&cpg CPG_MOD R9A07G054_CRU_ACLK>;
707 resets = <&cpg R9A07G054_CRU_PRESETN>,
708 <&cpg R9A07G054_CRU_ARESETN>;
710 power-domains = <&cpg>;
744 clocks = <&cpg CPG_MOD R9A07G054_CRU_SYSCLK>,
745 <&cpg CPG_MOD R9A07G054_CRU_VCLK>,
746 <&cpg CPG_MOD R9A07G054_CRU_PCLK>;
748 resets = <&cpg R9A07G054_CRU_PRESETN>,
749 <&cpg R9A07G054_CRU_CMN_RSTB>;
751 power-domains = <&cpg>;
788 clocks = <&cpg CPG_MOD R9A07G054_MIPI_DSI_PLLCLK>,
789 <&cpg CPG_MOD R9A07G054_MIPI_DSI_SYSCLK>,
790 <&cpg CPG_MOD R9A07G054_MIPI_DSI_ACLK>,
791 <&cpg CPG_MOD R9A07G054_MIPI_DSI_PCLK>,
792 <&cpg CPG_MOD R9A07G054_MIPI_DSI_VCLK>,
793 <&cpg CPG_MOD R9A07G054_MIPI_DSI_LPCLK>;
795 resets = <&cpg R9A07G054_MIPI_DSI_CMN_RSTB>,
796 <&cpg R9A07G054_MIPI_DSI_ARESET_N>,
797 <&cpg R9A07G054_MIPI_DSI_PRESET_N>;
799 power-domains = <&cpg>;
824 clocks = <&cpg CPG_MOD R9A07G054_LCDC_CLK_A>,
825 <&cpg CPG_MOD R9A07G054_LCDC_CLK_P>,
826 <&cpg CPG_MOD R9A07G054_LCDC_CLK_D>;
828 power-domains = <&cpg>;
829 resets = <&cpg R9A07G054_LCDC_RESET_N>;
837 clocks = <&cpg CPG_MOD R9A07G054_LCDC_CLK_A>,
838 <&cpg CPG_MOD R9A07G054_LCDC_CLK_P>,
839 <&cpg CPG_MOD R9A07G054_LCDC_CLK_D>;
841 power-domains = <&cpg>;
842 resets = <&cpg R9A07G054_LCDC_RESET_N>;
850 clocks = <&cpg CPG_MOD R9A07G054_LCDC_CLK_A>,
851 <&cpg CPG_MOD R9A07G054_LCDC_CLK_P>,
852 <&cpg CPG_MOD R9A07G054_LCDC_CLK_D>;
854 power-domains = <&cpg>;
855 resets = <&cpg R9A07G054_LCDC_RESET_N>;
876 cpg: clock-controller@11010000 { label
877 compatible = "renesas,r9a07g054-cpg";
908 clocks = <&cpg CPG_MOD R9A07G054_GPIO_HCLK>;
909 power-domains = <&cpg>;
910 resets = <&cpg R9A07G054_GPIO_RSTN>,
911 <&cpg R9A07G054_GPIO_PORT_RESETN>,
912 <&cpg R9A07G054_GPIO_SPARE_RESETN>;
983 clocks = <&cpg CPG_MOD R9A07G054_IA55_CLK>,
984 <&cpg CPG_MOD R9A07G054_IA55_PCLK>;
986 power-domains = <&cpg>;
987 resets = <&cpg R9A07G054_IA55_RESETN>;
1017 clocks = <&cpg CPG_MOD R9A07G054_DMAC_ACLK>,
1018 <&cpg CPG_MOD R9A07G054_DMAC_PCLK>;
1020 power-domains = <&cpg>;
1021 resets = <&cpg R9A07G054_DMAC_ARESETN>,
1022 <&cpg R9A07G054_DMAC_RST_ASYNC>;
1037 clocks = <&cpg CPG_MOD R9A07G054_GPU_CLK>,
1038 <&cpg CPG_MOD R9A07G054_GPU_AXI_CLK>,
1039 <&cpg CPG_MOD R9A07G054_GPU_ACE_CLK>;
1041 power-domains = <&cpg>;
1042 resets = <&cpg R9A07G054_GPU_RESETN>,
1043 <&cpg R9A07G054_GPU_AXI_RESETN>,
1044 <&cpg R9A07G054_GPU_ACE_RESETN>;
1065 clocks = <&cpg CPG_MOD R9A07G054_SDHI0_IMCLK>,
1066 <&cpg CPG_MOD R9A07G054_SDHI0_CLK_HS>,
1067 <&cpg CPG_MOD R9A07G054_SDHI0_IMCLK2>,
1068 <&cpg CPG_MOD R9A07G054_SDHI0_ACLK>;
1070 resets = <&cpg R9A07G054_SDHI0_IXRST>;
1071 power-domains = <&cpg>;
1081 clocks = <&cpg CPG_MOD R9A07G054_SDHI1_IMCLK>,
1082 <&cpg CPG_MOD R9A07G054_SDHI1_CLK_HS>,
1083 <&cpg CPG_MOD R9A07G054_SDHI1_IMCLK2>,
1084 <&cpg CPG_MOD R9A07G054_SDHI1_ACLK>;
1086 resets = <&cpg R9A07G054_SDHI1_IXRST>;
1087 power-domains = <&cpg>;
1100 clocks = <&cpg CPG_MOD R9A07G054_ETH0_CLK_AXI>,
1101 <&cpg CPG_MOD R9A07G054_ETH0_CLK_CHI>,
1102 <&cpg CPG_CORE R9A07G054_CLK_HP>;
1104 resets = <&cpg R9A07G054_ETH0_RST_HW_N>;
1105 power-domains = <&cpg>;
1120 clocks = <&cpg CPG_MOD R9A07G054_ETH1_CLK_AXI>,
1121 <&cpg CPG_MOD R9A07G054_ETH1_CLK_CHI>,
1122 <&cpg CPG_CORE R9A07G054_CLK_HP>;
1124 resets = <&cpg R9A07G054_ETH1_RST_HW_N>;
1125 power-domains = <&cpg>;
1135 clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>;
1136 resets = <&cpg R9A07G054_USB_PRESETN>;
1137 power-domains = <&cpg>;
1150 clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>,
1151 <&cpg CPG_MOD R9A07G054_USB_U2H0_HCLK>;
1153 <&cpg R9A07G054_USB_U2H0_HRESETN>;
1156 power-domains = <&cpg>;
1164 clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>,
1165 <&cpg CPG_MOD R9A07G054_USB_U2H1_HCLK>;
1167 <&cpg R9A07G054_USB_U2H1_HRESETN>;
1170 power-domains = <&cpg>;
1178 clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>,
1179 <&cpg CPG_MOD R9A07G054_USB_U2H0_HCLK>;
1181 <&cpg R9A07G054_USB_U2H0_HRESETN>;
1185 power-domains = <&cpg>;
1193 clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>,
1194 <&cpg CPG_MOD R9A07G054_USB_U2H1_HCLK>;
1196 <&cpg R9A07G054_USB_U2H1_HRESETN>;
1200 power-domains = <&cpg>;
1209 clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>,
1210 <&cpg CPG_MOD R9A07G054_USB_U2H0_HCLK>;
1213 power-domains = <&cpg>;
1222 clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>,
1223 <&cpg CPG_MOD R9A07G054_USB_U2H1_HCLK>;
1226 power-domains = <&cpg>;
1238 clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>,
1239 <&cpg CPG_MOD R9A07G054_USB_U2P_EXR_CPUCLK>;
1241 <&cpg R9A07G054_USB_U2P_EXL_SYSRST>;
1245 power-domains = <&cpg>;
1253 clocks = <&cpg CPG_MOD R9A07G054_WDT0_PCLK>,
1254 <&cpg CPG_MOD R9A07G054_WDT0_CLK>;
1259 resets = <&cpg R9A07G054_WDT0_PRESETN>;
1260 power-domains = <&cpg>;
1268 clocks = <&cpg CPG_MOD R9A07G054_WDT1_PCLK>,
1269 <&cpg CPG_MOD R9A07G054_WDT1_CLK>;
1274 resets = <&cpg R9A07G054_WDT1_PRESETN>;
1275 power-domains = <&cpg>;
1284 clocks = <&cpg CPG_MOD R9A07G054_OSTM0_PCLK>;
1285 resets = <&cpg R9A07G054_OSTM0_PRESETZ>;
1286 power-domains = <&cpg>;
1295 clocks = <&cpg CPG_MOD R9A07G054_OSTM1_PCLK>;
1296 resets = <&cpg R9A07G054_OSTM1_PRESETZ>;
1297 power-domains = <&cpg>;
1306 clocks = <&cpg CPG_MOD R9A07G054_OSTM2_PCLK>;
1307 resets = <&cpg R9A07G054_OSTM2_PRESETZ>;
1308 power-domains = <&cpg>;