Lines Matching full:cpg
9 #include <dt-bindings/clock/r9a07g044-cpg.h>
94 clocks = <&cpg CPG_CORE R9A07G044_CLK_I>;
104 clocks = <&cpg CPG_CORE R9A07G044_CLK_I>;
240 clocks = <&cpg CPG_MOD R9A07G044_MTU_X_MCK_MTU3>;
241 power-domains = <&cpg>;
242 resets = <&cpg R9A07G044_MTU_X_PRESET_MTU3>;
255 clocks = <&cpg CPG_MOD R9A07G044_SSI0_PCLK2>,
256 <&cpg CPG_MOD R9A07G044_SSI0_PCLK_SFR>,
259 resets = <&cpg R9A07G044_SSI0_RST_M2_REG>;
262 power-domains = <&cpg>;
275 clocks = <&cpg CPG_MOD R9A07G044_SSI1_PCLK2>,
276 <&cpg CPG_MOD R9A07G044_SSI1_PCLK_SFR>,
279 resets = <&cpg R9A07G044_SSI1_RST_M2_REG>;
282 power-domains = <&cpg>;
294 clocks = <&cpg CPG_MOD R9A07G044_SSI2_PCLK2>,
295 <&cpg CPG_MOD R9A07G044_SSI2_PCLK_SFR>,
298 resets = <&cpg R9A07G044_SSI2_RST_M2_REG>;
301 power-domains = <&cpg>;
314 clocks = <&cpg CPG_MOD R9A07G044_SSI3_PCLK2>,
315 <&cpg CPG_MOD R9A07G044_SSI3_PCLK_SFR>,
318 resets = <&cpg R9A07G044_SSI3_RST_M2_REG>;
321 power-domains = <&cpg>;
333 clocks = <&cpg CPG_MOD R9A07G044_RSPI0_CLKB>;
334 resets = <&cpg R9A07G044_RSPI0_RST>;
337 power-domains = <&cpg>;
351 clocks = <&cpg CPG_MOD R9A07G044_RSPI1_CLKB>;
352 resets = <&cpg R9A07G044_RSPI1_RST>;
355 power-domains = <&cpg>;
369 clocks = <&cpg CPG_MOD R9A07G044_RSPI2_CLKB>;
370 resets = <&cpg R9A07G044_RSPI2_RST>;
373 power-domains = <&cpg>;
391 clocks = <&cpg CPG_MOD R9A07G044_SCIF0_CLK_PCK>;
393 power-domains = <&cpg>;
394 resets = <&cpg R9A07G044_SCIF0_RST_SYSTEM_N>;
409 clocks = <&cpg CPG_MOD R9A07G044_SCIF1_CLK_PCK>;
411 power-domains = <&cpg>;
412 resets = <&cpg R9A07G044_SCIF1_RST_SYSTEM_N>;
427 clocks = <&cpg CPG_MOD R9A07G044_SCIF2_CLK_PCK>;
429 power-domains = <&cpg>;
430 resets = <&cpg R9A07G044_SCIF2_RST_SYSTEM_N>;
445 clocks = <&cpg CPG_MOD R9A07G044_SCIF3_CLK_PCK>;
447 power-domains = <&cpg>;
448 resets = <&cpg R9A07G044_SCIF3_RST_SYSTEM_N>;
463 clocks = <&cpg CPG_MOD R9A07G044_SCIF4_CLK_PCK>;
465 power-domains = <&cpg>;
466 resets = <&cpg R9A07G044_SCIF4_RST_SYSTEM_N>;
478 clocks = <&cpg CPG_MOD R9A07G044_SCI0_CLKP>;
480 power-domains = <&cpg>;
481 resets = <&cpg R9A07G044_SCI0_RST>;
493 clocks = <&cpg CPG_MOD R9A07G044_SCI1_CLKP>;
495 power-domains = <&cpg>;
496 resets = <&cpg R9A07G044_SCI1_RST>;
514 clocks = <&cpg CPG_MOD R9A07G044_CANFD_PCLK>,
515 <&cpg CPG_CORE R9A07G044_CLK_P0_DIV2>,
518 assigned-clocks = <&cpg CPG_CORE R9A07G044_CLK_P0_DIV2>;
520 resets = <&cpg R9A07G044_CANFD_RSTP_N>,
521 <&cpg R9A07G044_CANFD_RSTC_N>;
523 power-domains = <&cpg>;
549 clocks = <&cpg CPG_MOD R9A07G044_I2C0_PCLK>;
551 resets = <&cpg R9A07G044_I2C0_MRST>;
552 power-domains = <&cpg>;
571 clocks = <&cpg CPG_MOD R9A07G044_I2C1_PCLK>;
573 resets = <&cpg R9A07G044_I2C1_MRST>;
574 power-domains = <&cpg>;
593 clocks = <&cpg CPG_MOD R9A07G044_I2C2_PCLK>;
595 resets = <&cpg R9A07G044_I2C2_MRST>;
596 power-domains = <&cpg>;
615 clocks = <&cpg CPG_MOD R9A07G044_I2C3_PCLK>;
617 resets = <&cpg R9A07G044_I2C3_MRST>;
618 power-domains = <&cpg>;
626 clocks = <&cpg CPG_MOD R9A07G044_ADC_ADCLK>,
627 <&cpg CPG_MOD R9A07G044_ADC_PCLK>;
629 resets = <&cpg R9A07G044_ADC_PRESETN>,
630 <&cpg R9A07G044_ADC_ADRST_N>;
632 power-domains = <&cpg>;
668 clocks = <&cpg CPG_MOD R9A07G044_TSU_PCLK>;
669 resets = <&cpg R9A07G044_TSU_PRESETN>;
670 power-domains = <&cpg>;
682 clocks = <&cpg CPG_MOD R9A07G044_SPI_CLK2>,
683 <&cpg CPG_MOD R9A07G044_SPI_CLK>;
684 resets = <&cpg R9A07G044_SPI_RST>;
685 power-domains = <&cpg>;
694 clocks = <&cpg CPG_MOD R9A07G044_CRU_VCLK>,
695 <&cpg CPG_MOD R9A07G044_CRU_PCLK>,
696 <&cpg CPG_MOD R9A07G044_CRU_ACLK>;
702 resets = <&cpg R9A07G044_CRU_PRESETN>,
703 <&cpg R9A07G044_CRU_ARESETN>;
705 power-domains = <&cpg>;
739 clocks = <&cpg CPG_MOD R9A07G044_CRU_SYSCLK>,
740 <&cpg CPG_MOD R9A07G044_CRU_VCLK>,
741 <&cpg CPG_MOD R9A07G044_CRU_PCLK>;
743 resets = <&cpg R9A07G044_CRU_PRESETN>,
744 <&cpg R9A07G044_CRU_CMN_RSTB>;
746 power-domains = <&cpg>;
783 clocks = <&cpg CPG_MOD R9A07G044_MIPI_DSI_PLLCLK>,
784 <&cpg CPG_MOD R9A07G044_MIPI_DSI_SYSCLK>,
785 <&cpg CPG_MOD R9A07G044_MIPI_DSI_ACLK>,
786 <&cpg CPG_MOD R9A07G044_MIPI_DSI_PCLK>,
787 <&cpg CPG_MOD R9A07G044_MIPI_DSI_VCLK>,
788 <&cpg CPG_MOD R9A07G044_MIPI_DSI_LPCLK>;
790 resets = <&cpg R9A07G044_MIPI_DSI_CMN_RSTB>,
791 <&cpg R9A07G044_MIPI_DSI_ARESET_N>,
792 <&cpg R9A07G044_MIPI_DSI_PRESET_N>;
794 power-domains = <&cpg>;
818 clocks = <&cpg CPG_MOD R9A07G044_LCDC_CLK_A>,
819 <&cpg CPG_MOD R9A07G044_LCDC_CLK_P>,
820 <&cpg CPG_MOD R9A07G044_LCDC_CLK_D>;
822 power-domains = <&cpg>;
823 resets = <&cpg R9A07G044_LCDC_RESET_N>;
831 clocks = <&cpg CPG_MOD R9A07G044_LCDC_CLK_A>,
832 <&cpg CPG_MOD R9A07G044_LCDC_CLK_P>,
833 <&cpg CPG_MOD R9A07G044_LCDC_CLK_D>;
835 power-domains = <&cpg>;
836 resets = <&cpg R9A07G044_LCDC_RESET_N>;
843 clocks = <&cpg CPG_MOD R9A07G044_LCDC_CLK_A>,
844 <&cpg CPG_MOD R9A07G044_LCDC_CLK_P>,
845 <&cpg CPG_MOD R9A07G044_LCDC_CLK_D>;
847 power-domains = <&cpg>;
848 resets = <&cpg R9A07G044_LCDC_RESET_N>;
869 cpg: clock-controller@11010000 { label
870 compatible = "renesas,r9a07g044-cpg";
900 clocks = <&cpg CPG_MOD R9A07G044_GPIO_HCLK>;
901 power-domains = <&cpg>;
902 resets = <&cpg R9A07G044_GPIO_RSTN>,
903 <&cpg R9A07G044_GPIO_PORT_RESETN>,
904 <&cpg R9A07G044_GPIO_SPARE_RESETN>;
975 clocks = <&cpg CPG_MOD R9A07G044_IA55_CLK>,
976 <&cpg CPG_MOD R9A07G044_IA55_PCLK>;
978 power-domains = <&cpg>;
979 resets = <&cpg R9A07G044_IA55_RESETN>;
1009 clocks = <&cpg CPG_MOD R9A07G044_DMAC_ACLK>,
1010 <&cpg CPG_MOD R9A07G044_DMAC_PCLK>;
1012 power-domains = <&cpg>;
1013 resets = <&cpg R9A07G044_DMAC_ARESETN>,
1014 <&cpg R9A07G044_DMAC_RST_ASYNC>;
1029 clocks = <&cpg CPG_MOD R9A07G044_GPU_CLK>,
1030 <&cpg CPG_MOD R9A07G044_GPU_AXI_CLK>,
1031 <&cpg CPG_MOD R9A07G044_GPU_ACE_CLK>;
1033 power-domains = <&cpg>;
1034 resets = <&cpg R9A07G044_GPU_RESETN>,
1035 <&cpg R9A07G044_GPU_AXI_RESETN>,
1036 <&cpg R9A07G044_GPU_ACE_RESETN>;
1057 clocks = <&cpg CPG_MOD R9A07G044_SDHI0_IMCLK>,
1058 <&cpg CPG_MOD R9A07G044_SDHI0_CLK_HS>,
1059 <&cpg CPG_MOD R9A07G044_SDHI0_IMCLK2>,
1060 <&cpg CPG_MOD R9A07G044_SDHI0_ACLK>;
1062 resets = <&cpg R9A07G044_SDHI0_IXRST>;
1063 power-domains = <&cpg>;
1073 clocks = <&cpg CPG_MOD R9A07G044_SDHI1_IMCLK>,
1074 <&cpg CPG_MOD R9A07G044_SDHI1_CLK_HS>,
1075 <&cpg CPG_MOD R9A07G044_SDHI1_IMCLK2>,
1076 <&cpg CPG_MOD R9A07G044_SDHI1_ACLK>;
1078 resets = <&cpg R9A07G044_SDHI1_IXRST>;
1079 power-domains = <&cpg>;
1092 clocks = <&cpg CPG_MOD R9A07G044_ETH0_CLK_AXI>,
1093 <&cpg CPG_MOD R9A07G044_ETH0_CLK_CHI>,
1094 <&cpg CPG_CORE R9A07G044_CLK_HP>;
1096 resets = <&cpg R9A07G044_ETH0_RST_HW_N>;
1097 power-domains = <&cpg>;
1112 clocks = <&cpg CPG_MOD R9A07G044_ETH1_CLK_AXI>,
1113 <&cpg CPG_MOD R9A07G044_ETH1_CLK_CHI>,
1114 <&cpg CPG_CORE R9A07G044_CLK_HP>;
1116 resets = <&cpg R9A07G044_ETH1_RST_HW_N>;
1117 power-domains = <&cpg>;
1127 clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>;
1128 resets = <&cpg R9A07G044_USB_PRESETN>;
1129 power-domains = <&cpg>;
1142 clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
1143 <&cpg CPG_MOD R9A07G044_USB_U2H0_HCLK>;
1145 <&cpg R9A07G044_USB_U2H0_HRESETN>;
1148 power-domains = <&cpg>;
1156 clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
1157 <&cpg CPG_MOD R9A07G044_USB_U2H1_HCLK>;
1159 <&cpg R9A07G044_USB_U2H1_HRESETN>;
1162 power-domains = <&cpg>;
1170 clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
1171 <&cpg CPG_MOD R9A07G044_USB_U2H0_HCLK>;
1173 <&cpg R9A07G044_USB_U2H0_HRESETN>;
1177 power-domains = <&cpg>;
1185 clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
1186 <&cpg CPG_MOD R9A07G044_USB_U2H1_HCLK>;
1188 <&cpg R9A07G044_USB_U2H1_HRESETN>;
1192 power-domains = <&cpg>;
1201 clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
1202 <&cpg CPG_MOD R9A07G044_USB_U2H0_HCLK>;
1205 power-domains = <&cpg>;
1214 clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
1215 <&cpg CPG_MOD R9A07G044_USB_U2H1_HCLK>;
1218 power-domains = <&cpg>;
1230 clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
1231 <&cpg CPG_MOD R9A07G044_USB_U2P_EXR_CPUCLK>;
1233 <&cpg R9A07G044_USB_U2P_EXL_SYSRST>;
1237 power-domains = <&cpg>;
1245 clocks = <&cpg CPG_MOD R9A07G044_WDT0_PCLK>,
1246 <&cpg CPG_MOD R9A07G044_WDT0_CLK>;
1251 resets = <&cpg R9A07G044_WDT0_PRESETN>;
1252 power-domains = <&cpg>;
1260 clocks = <&cpg CPG_MOD R9A07G044_WDT1_PCLK>,
1261 <&cpg CPG_MOD R9A07G044_WDT1_CLK>;
1266 resets = <&cpg R9A07G044_WDT1_PRESETN>;
1267 power-domains = <&cpg>;
1276 clocks = <&cpg CPG_MOD R9A07G044_OSTM0_PCLK>;
1277 resets = <&cpg R9A07G044_OSTM0_PRESETZ>;
1278 power-domains = <&cpg>;
1287 clocks = <&cpg CPG_MOD R9A07G044_OSTM1_PCLK>;
1288 resets = <&cpg R9A07G044_OSTM1_PRESETZ>;
1289 power-domains = <&cpg>;
1298 clocks = <&cpg CPG_MOD R9A07G044_OSTM2_PCLK>;
1299 resets = <&cpg R9A07G044_OSTM2_PRESETZ>;
1300 power-domains = <&cpg>;