Lines Matching full:cpg
8 #include <dt-bindings/clock/r9a07g043-cpg.h>
140 clocks = <&cpg CPG_MOD R9A07G043_MTU_X_MCK_MTU3>;
141 power-domains = <&cpg>;
142 resets = <&cpg R9A07G043_MTU_X_PRESET_MTU3>;
155 clocks = <&cpg CPG_MOD R9A07G043_SSI0_PCLK2>,
156 <&cpg CPG_MOD R9A07G043_SSI0_PCLK_SFR>,
159 resets = <&cpg R9A07G043_SSI0_RST_M2_REG>;
162 power-domains = <&cpg>;
175 clocks = <&cpg CPG_MOD R9A07G043_SSI1_PCLK2>,
176 <&cpg CPG_MOD R9A07G043_SSI1_PCLK_SFR>,
179 resets = <&cpg R9A07G043_SSI1_RST_M2_REG>;
182 power-domains = <&cpg>;
194 clocks = <&cpg CPG_MOD R9A07G043_SSI2_PCLK2>,
195 <&cpg CPG_MOD R9A07G043_SSI2_PCLK_SFR>,
198 resets = <&cpg R9A07G043_SSI2_RST_M2_REG>;
201 power-domains = <&cpg>;
214 clocks = <&cpg CPG_MOD R9A07G043_SSI3_PCLK2>,
215 <&cpg CPG_MOD R9A07G043_SSI3_PCLK_SFR>,
218 resets = <&cpg R9A07G043_SSI3_RST_M2_REG>;
221 power-domains = <&cpg>;
233 clocks = <&cpg CPG_MOD R9A07G043_RSPI0_CLKB>;
234 resets = <&cpg R9A07G043_RSPI0_RST>;
237 power-domains = <&cpg>;
251 clocks = <&cpg CPG_MOD R9A07G043_RSPI1_CLKB>;
252 resets = <&cpg R9A07G043_RSPI1_RST>;
255 power-domains = <&cpg>;
269 clocks = <&cpg CPG_MOD R9A07G043_RSPI2_CLKB>;
270 resets = <&cpg R9A07G043_RSPI2_RST>;
273 power-domains = <&cpg>;
292 clocks = <&cpg CPG_MOD R9A07G043_SCIF0_CLK_PCK>;
294 power-domains = <&cpg>;
295 resets = <&cpg R9A07G043_SCIF0_RST_SYSTEM_N>;
311 clocks = <&cpg CPG_MOD R9A07G043_SCIF1_CLK_PCK>;
313 power-domains = <&cpg>;
314 resets = <&cpg R9A07G043_SCIF1_RST_SYSTEM_N>;
330 clocks = <&cpg CPG_MOD R9A07G043_SCIF2_CLK_PCK>;
332 power-domains = <&cpg>;
333 resets = <&cpg R9A07G043_SCIF2_RST_SYSTEM_N>;
349 clocks = <&cpg CPG_MOD R9A07G043_SCIF3_CLK_PCK>;
351 power-domains = <&cpg>;
352 resets = <&cpg R9A07G043_SCIF3_RST_SYSTEM_N>;
368 clocks = <&cpg CPG_MOD R9A07G043_SCIF4_CLK_PCK>;
370 power-domains = <&cpg>;
371 resets = <&cpg R9A07G043_SCIF4_RST_SYSTEM_N>;
383 clocks = <&cpg CPG_MOD R9A07G043_SCI0_CLKP>;
385 power-domains = <&cpg>;
386 resets = <&cpg R9A07G043_SCI0_RST>;
398 clocks = <&cpg CPG_MOD R9A07G043_SCI1_CLKP>;
400 power-domains = <&cpg>;
401 resets = <&cpg R9A07G043_SCI1_RST>;
419 clocks = <&cpg CPG_MOD R9A07G043_CANFD_PCLK>,
420 <&cpg CPG_CORE R9A07G043_CLK_P0_DIV2>,
423 assigned-clocks = <&cpg CPG_CORE R9A07G043_CLK_P0_DIV2>;
425 resets = <&cpg R9A07G043_CANFD_RSTP_N>,
426 <&cpg R9A07G043_CANFD_RSTC_N>;
428 power-domains = <&cpg>;
454 clocks = <&cpg CPG_MOD R9A07G043_I2C0_PCLK>;
456 resets = <&cpg R9A07G043_I2C0_MRST>;
457 power-domains = <&cpg>;
476 clocks = <&cpg CPG_MOD R9A07G043_I2C1_PCLK>;
478 resets = <&cpg R9A07G043_I2C1_MRST>;
479 power-domains = <&cpg>;
498 clocks = <&cpg CPG_MOD R9A07G043_I2C2_PCLK>;
500 resets = <&cpg R9A07G043_I2C2_MRST>;
501 power-domains = <&cpg>;
520 clocks = <&cpg CPG_MOD R9A07G043_I2C3_PCLK>;
522 resets = <&cpg R9A07G043_I2C3_MRST>;
523 power-domains = <&cpg>;
531 clocks = <&cpg CPG_MOD R9A07G043_ADC_ADCLK>,
532 <&cpg CPG_MOD R9A07G043_ADC_PCLK>;
534 resets = <&cpg R9A07G043_ADC_PRESETN>,
535 <&cpg R9A07G043_ADC_ADRST_N>;
537 power-domains = <&cpg>;
555 clocks = <&cpg CPG_MOD R9A07G043_TSU_PCLK>;
556 resets = <&cpg R9A07G043_TSU_PRESETN>;
557 power-domains = <&cpg>;
568 clocks = <&cpg CPG_MOD R9A07G043_SPI_CLK2>,
569 <&cpg CPG_MOD R9A07G043_SPI_CLK>;
570 resets = <&cpg R9A07G043_SPI_RST>;
571 power-domains = <&cpg>;
577 cpg: clock-controller@11010000 { label
578 compatible = "renesas,r9a07g043-cpg";
602 clocks = <&cpg CPG_MOD R9A07G043_GPIO_HCLK>;
603 power-domains = <&cpg>;
604 resets = <&cpg R9A07G043_GPIO_RSTN>,
605 <&cpg R9A07G043_GPIO_PORT_RESETN>,
606 <&cpg R9A07G043_GPIO_SPARE_RESETN>;
636 clocks = <&cpg CPG_MOD R9A07G043_DMAC_ACLK>,
637 <&cpg CPG_MOD R9A07G043_DMAC_PCLK>;
639 power-domains = <&cpg>;
640 resets = <&cpg R9A07G043_DMAC_ARESETN>,
641 <&cpg R9A07G043_DMAC_RST_ASYNC>;
653 clocks = <&cpg CPG_MOD R9A07G043_SDHI0_IMCLK>,
654 <&cpg CPG_MOD R9A07G043_SDHI0_CLK_HS>,
655 <&cpg CPG_MOD R9A07G043_SDHI0_IMCLK2>,
656 <&cpg CPG_MOD R9A07G043_SDHI0_ACLK>;
658 resets = <&cpg R9A07G043_SDHI0_IXRST>;
659 power-domains = <&cpg>;
669 clocks = <&cpg CPG_MOD R9A07G043_SDHI1_IMCLK>,
670 <&cpg CPG_MOD R9A07G043_SDHI1_CLK_HS>,
671 <&cpg CPG_MOD R9A07G043_SDHI1_IMCLK2>,
672 <&cpg CPG_MOD R9A07G043_SDHI1_ACLK>;
674 resets = <&cpg R9A07G043_SDHI1_IXRST>;
675 power-domains = <&cpg>;
688 clocks = <&cpg CPG_MOD R9A07G043_ETH0_CLK_AXI>,
689 <&cpg CPG_MOD R9A07G043_ETH0_CLK_CHI>,
690 <&cpg CPG_CORE R9A07G043_CLK_HP>;
692 resets = <&cpg R9A07G043_ETH0_RST_HW_N>;
693 power-domains = <&cpg>;
708 clocks = <&cpg CPG_MOD R9A07G043_ETH1_CLK_AXI>,
709 <&cpg CPG_MOD R9A07G043_ETH1_CLK_CHI>,
710 <&cpg CPG_CORE R9A07G043_CLK_HP>;
712 resets = <&cpg R9A07G043_ETH1_RST_HW_N>;
713 power-domains = <&cpg>;
723 clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>;
724 resets = <&cpg R9A07G043_USB_PRESETN>;
725 power-domains = <&cpg>;
738 clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>,
739 <&cpg CPG_MOD R9A07G043_USB_U2H0_HCLK>;
741 <&cpg R9A07G043_USB_U2H0_HRESETN>;
744 power-domains = <&cpg>;
752 clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>,
753 <&cpg CPG_MOD R9A07G043_USB_U2H1_HCLK>;
755 <&cpg R9A07G043_USB_U2H1_HRESETN>;
758 power-domains = <&cpg>;
766 clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>,
767 <&cpg CPG_MOD R9A07G043_USB_U2H0_HCLK>;
769 <&cpg R9A07G043_USB_U2H0_HRESETN>;
773 power-domains = <&cpg>;
781 clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>,
782 <&cpg CPG_MOD R9A07G043_USB_U2H1_HCLK>;
784 <&cpg R9A07G043_USB_U2H1_HRESETN>;
788 power-domains = <&cpg>;
797 clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>,
798 <&cpg CPG_MOD R9A07G043_USB_U2H0_HCLK>;
801 power-domains = <&cpg>;
810 clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>,
811 <&cpg CPG_MOD R9A07G043_USB_U2H1_HCLK>;
814 power-domains = <&cpg>;
826 clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>,
827 <&cpg CPG_MOD R9A07G043_USB_U2P_EXR_CPUCLK>;
829 <&cpg R9A07G043_USB_U2P_EXL_SYSRST>;
833 power-domains = <&cpg>;
841 clocks = <&cpg CPG_MOD R9A07G043_WDT0_PCLK>,
842 <&cpg CPG_MOD R9A07G043_WDT0_CLK>;
847 resets = <&cpg R9A07G043_WDT0_PRESETN>;
848 power-domains = <&cpg>;
857 clocks = <&cpg CPG_MOD R9A07G043_OSTM0_PCLK>;
858 resets = <&cpg R9A07G043_OSTM0_PRESETZ>;
859 power-domains = <&cpg>;
868 clocks = <&cpg CPG_MOD R9A07G043_OSTM1_PCLK>;
869 resets = <&cpg R9A07G043_OSTM1_PRESETZ>;
870 power-domains = <&cpg>;
879 clocks = <&cpg CPG_MOD R9A07G043_OSTM2_PCLK>;
880 resets = <&cpg R9A07G043_OSTM2_PRESETZ>;
881 power-domains = <&cpg>;