Lines Matching +full:0 +full:x040000
49 #size-cells = <0>;
51 port@0 {
52 reg = <0>;
70 reg = <0 0x48000000 0 0x78000000>;
75 #clock-cells = <0>;
79 vcc1v8_d4: regulator-0 {
101 clock-names = "du.0", "dclkin.0";
114 pinctrl-0 = <&gether_pins>;
122 phy0: ethernet-phy@0 {
126 reg = <0>;
134 pinctrl-0 = <&i2c0_pins>;
142 #sound-dai-cells = <0>;
143 reg = <0x39>;
158 #size-cells = <0>;
160 port@0 {
161 reg = <0>;
218 pinctrl-0 = <&qspi0_pins>;
223 flash@0 {
225 reg = <0>;
234 bootparam@0 {
235 reg = <0x00000000 0x040000>;
239 reg = <0x00040000 0x080000>;
243 reg = <0x000c0000 0x080000>;
247 reg = <0x00140000 0x040000>;
251 reg = <0x00180000 0x040000>;
255 reg = <0x001c0000 0x460000>;
259 reg = <0x00640000 0x0c0000>;
263 reg = <0x00700000 0x040000>;
267 reg = <0x00740000 0x080000>;
270 reg = <0x007c0000 0x1400000>;
273 reg = <0x01bc0000 0x2440000>;
285 pinctrl-0 = <&scif0_pins>, <&scif_clk_pins>;