Lines Matching +full:0 +full:x040000
68 #size-cells = <0>;
70 port@0 {
71 reg = <0>;
89 reg = <0x0 0x48000000 0x0 0x38000000>;
94 #clock-cells = <0>;
100 pinctrl-0 = <&avb_pins>;
109 phy0: ethernet-phy@0 {
113 reg = <0>;
121 pinctrl-0 = <&canfd0_pins>;
134 port@0 {
136 clock-lanes = <0>;
146 clock-names = "du.0", "dclkin.0";
159 pinctrl-0 = <&i2c0_pins>;
167 reg = <0x20>;
174 reg = <0x39>;
190 #size-cells = <0>;
192 port@0 {
193 reg = <0>;
210 pinctrl-0 = <&i2c3_pins>;
218 reg = <0x48>;
220 maxim,gpio-poc = <0 GPIO_ACTIVE_LOW>;
221 enable-gpios = <&io_expander 0 GPIO_ACTIVE_HIGH>;
225 #size-cells = <0>;
227 port@0 {
228 reg = <0>;
246 clock-lanes = <0>;
255 #size-cells = <0>;
257 i2c@0 {
259 #size-cells = <0>;
260 reg = <0>;
267 #size-cells = <0>;
275 #size-cells = <0>;
283 #size-cells = <0>;
305 pinctrl-0 = <&scif_clk_pins>;
345 pinctrl-0 = <&qspi0_pins>;
350 flash@0 {
352 reg = <0>;
361 bootparam@0 {
362 reg = <0x00000000 0x040000>;
366 reg = <0x00040000 0x080000>;
370 reg = <0x000c0000 0x080000>;
374 reg = <0x00140000 0x040000>;
378 reg = <0x00180000 0x040000>;
382 reg = <0x001c0000 0x460000>;
386 reg = <0x00640000 0x0c0000>;
390 reg = <0x00700000 0x040000>;
394 reg = <0x00740000 0x080000>;
397 reg = <0x007c0000 0x1400000>;
400 reg = <0x01bc0000 0x2440000>;
412 pinctrl-0 = <&scif0_pins>;