Lines Matching +full:0 +full:x040000
36 d3_3v: regulator-0 {
62 #size-cells = <0>;
64 port@0 {
65 reg = <0>;
83 reg = <0 0x48000000 0 0x78000000>;
97 #clock-cells = <0>;
103 pinctrl-0 = <&canfd0_pins>;
116 port@0 {
118 clock-lanes = <0>;
130 port@0 {
132 clock-lanes = <0>;
143 clock-names = "du.0", "dclkin.0";
156 pinctrl-0 = <&gether_pins>;
164 phy0: ethernet-phy@0 {
168 reg = <0>;
176 pinctrl-0 = <&i2c0_pins>;
184 reg = <0x20>;
191 reg = <0x21>;
198 reg = <0x39>;
213 #size-cells = <0>;
215 port@0 {
216 reg = <0>;
233 reg = <0x50>;
239 pinctrl-0 = <&i2c1_pins>;
247 reg = <0x48>;
249 maxim,gpio-poc = <0 GPIO_ACTIVE_LOW>;
250 enable-gpios = <&io_expander0 0 GPIO_ACTIVE_HIGH>;
254 #size-cells = <0>;
256 port@0 {
257 reg = <0>;
275 clock-lanes = <0>;
284 #size-cells = <0>;
286 i2c@0 {
288 #size-cells = <0>;
289 reg = <0>;
296 #size-cells = <0>;
304 #size-cells = <0>;
312 #size-cells = <0>;
322 reg = <0x4a>;
324 maxim,gpio-poc = <0 GPIO_ACTIVE_LOW>;
325 enable-gpios = <&io_expander1 0 GPIO_ACTIVE_HIGH>;
329 #size-cells = <0>;
331 port@0 {
332 reg = <0>;
350 clock-lanes = <0>;
359 #size-cells = <0>;
361 i2c@0 {
363 #size-cells = <0>;
364 reg = <0>;
371 #size-cells = <0>;
379 #size-cells = <0>;
387 #size-cells = <0>;
409 pinctrl-0 = <&mmc_pins>;
480 pinctrl-0 = <&qspi0_pins>;
485 flash@0 {
487 reg = <0>;
496 bootparam@0 {
497 reg = <0x00000000 0x040000>;
501 reg = <0x00040000 0x080000>;
505 reg = <0x000c0000 0x080000>;
509 reg = <0x00140000 0x040000>;
513 reg = <0x00180000 0x040000>;
517 reg = <0x001c0000 0x460000>;
521 reg = <0x00640000 0x0c0000>;
525 reg = <0x00700000 0x040000>;
529 reg = <0x00740000 0x080000>;
532 reg = <0x007c0000 0x1400000>;
535 reg = <0x01bc0000 0x2440000>;
547 pinctrl-0 = <&scif0_pins>, <&scif_clk_pins>;