dts/qcom/sm8650.dtsi

53 			clock-mult = <1>;
62 			clock-mult = <1>;
203 			clocks = <&cpufreq_hw 1>;
213 			qcom,freq-domain = <&cpufreq_hw 1>;
230 			clocks = <&cpufreq_hw 1>;
240 			qcom,freq-domain = <&cpufreq_hw 1>;
328 			GOLD_CPU_SLEEP_0: cpu-sleep-1-0 {
358 			CLUSTER_SLEEP_1: cluster-sleep-1 {
383 	mc_virt: interconnect-1 {
633 			qcom,client-id = <1>;
680 			#qcom,smem-state-cells = <1>;
706 			#qcom,smem-state-cells = <1>;
728 		qcom,remote-pid = <1>;
732 			#qcom,smem-state-cells = <1>;
743 			#qcom,smem-state-cells = <1>;
772 				 <&ufs_mem_phy 1>,
776 			#clock-cells = <1>;
777 			#reset-cells = <1>;
778 			#power-domain-cells = <1>;
859 				       <&gpi_dma2 1 0 QCOM_GPI_I2C>;
866 				#address-cells = <1>;
892 				       <&gpi_dma2 1 0 QCOM_GPI_SPI>;
899 				#address-cells = <1>;
924 				dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
925 				       <&gpi_dma2 1 1 QCOM_GPI_I2C>;
932 				#address-cells = <1>;
957 				dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
958 				       <&gpi_dma2 1 1 QCOM_GPI_SPI>;
965 				#address-cells = <1>;
991 				       <&gpi_dma2 1 2 QCOM_GPI_I2C>;
998 				#address-cells = <1>;
1024 				       <&gpi_dma2 1 2 QCOM_GPI_SPI>;
1031 				#address-cells = <1>;
1057 				       <&gpi_dma2 1 3 QCOM_GPI_I2C>;
1064 				#address-cells = <1>;
1090 				       <&gpi_dma2 1 3 QCOM_GPI_SPI>;
1097 				#address-cells = <1>;
1123 				       <&gpi_dma2 1 4 QCOM_GPI_I2C>;
1130 				#address-cells = <1>;
1156 				       <&gpi_dma2 1 4 QCOM_GPI_SPI>;
1163 				#address-cells = <1>;
1189 				       <&gpi_dma2 1 5 QCOM_GPI_I2C>;
1196 				#address-cells = <1>;
1222 				       <&gpi_dma2 1 5 QCOM_GPI_SPI>;
1229 				#address-cells = <1>;
1314 				#address-cells = <1>;
1341 				#address-cells = <1>;
1368 				#address-cells = <1>;
1395 				#address-cells = <1>;
1422 				#address-cells = <1>;
1449 				#address-cells = <1>;
1476 				#address-cells = <1>;
1503 				#address-cells = <1>;
1530 				#address-cells = <1>;
1557 				#address-cells = <1>;
1634 				       <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1641 				#address-cells = <1>;
1667 				       <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1674 				#address-cells = <1>;
1699 				dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1700 				       <&gpi_dma1 1 1 QCOM_GPI_I2C>;
1707 				#address-cells = <1>;
1732 				dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1733 				       <&gpi_dma1 1 1 QCOM_GPI_SPI>;
1740 				#address-cells = <1>;
1766 				       <&gpi_dma1 1 2 QCOM_GPI_I2C>;
1773 				#address-cells = <1>;
1799 				       <&gpi_dma1 1 2 QCOM_GPI_SPI>;
1806 				#address-cells = <1>;
1832 				       <&gpi_dma1 1 3 QCOM_GPI_I2C>;
1839 				#address-cells = <1>;
1865 				       <&gpi_dma1 1 3 QCOM_GPI_SPI>;
1872 				#address-cells = <1>;
1898 				       <&gpi_dma1 1 4 QCOM_GPI_I2C>;
1905 				#address-cells = <1>;
1931 				       <&gpi_dma1 1 4 QCOM_GPI_SPI>;
1938 				#address-cells = <1>;
1964 				       <&gpi_dma1 1 5 QCOM_GPI_I2C>;
1971 				#address-cells = <1>;
1997 				       <&gpi_dma1 1 5 QCOM_GPI_SPI>;
2004 				#address-cells = <1>;
2030 				       <&gpi_dma1 1 6 QCOM_GPI_I2C>;
2037 				#address-cells = <1>;
2063 				       <&gpi_dma1 1 6 QCOM_GPI_SPI>;
2070 				#address-cells = <1>;
2096 				       <&gpi_dma1 1 7 QCOM_GPI_I2C>;
2103 				#address-cells = <1>;
2129 				       <&gpi_dma1 1 7 QCOM_GPI_SPI>;
2136 				#address-cells = <1>;
2219 		pcie0: pcie@1c00000 {
2278 			interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>,
2283 			#interrupt-cells = <1>;
2316 		pcie0_phy: phy@1c06000 {
2347 		pcie1: pcie@1c08000 {
2415 			interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>,
2420 			#interrupt-cells = <1>;
2426 			linux,pci-domain = <1>;
2453 		pcie1_phy: phy@1c0e000 {
2478 			#clock-cells = <1>;
2486 		cryptobam: dma-controller@1dc4000 {
2492 			#dma-cells = <1>;
2501 		crypto: crypto@1dfa000 {
2516 		ufs_mem_phy: phy@1d80000 {
2532 			#clock-cells = <1>;
2538 		ufs_mem_hc: ufs@1d84000 {
2590 			#reset-cells = <1>;
2595 		ice: crypto@1d88000 {
2603 		tcsr_mutex: hwlock@1f40000 {
2607 			#hwlock-cells = <1>;
2610 		tcsr: clock-controller@1fc0000 {
2616 			#clock-cells = <1>;
2617 			#reset-cells = <1>;
2632 				 <&adreno_smmu 1 0x0>;
2766 			#clock-cells = <1>;
2767 			#reset-cells = <1>;
2768 			#power-domain-cells = <1>;
2776 			#global-interrupts = <1>;
2830 					      <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>;
2847 					   <&ipa_smp2p_out 1>;
2860 					      <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>,
2901 				qcom,remote-pid = <1>;
2921 			#sound-dai-cells = <1>;
2950 			#sound-dai-cells = <1>;
2968 			#sound-dai-cells = <1>;
2997 			#sound-dai-cells = <1>;
3015 			#sound-dai-cells = <1>;
3032 			#sound-dai-cells = <1>;
3061 			#sound-dai-cells = <1>;
3093 			#sound-dai-cells = <1>;
3109 			#sound-dai-cells = <1>;
3129 					slew-rate = <1>;
3137 					slew-rate = <1>;
3147 					slew-rate = <1>;
3155 					slew-rate = <1>;
3197 					slew-rate = <1>;
3205 					slew-rate = <1>;
3215 					slew-rate = <1>;
3223 					slew-rate = <1>;
3327 			#clock-cells = <1>;
3328 			#reset-cells = <1>;
3329 			#power-domain-cells = <1>;
3344 			pinctrl-1 = <&cci0_0_sleep &cci0_1_sleep>;
3347 			#address-cells = <1>;
3353 				#address-cells = <1>;
3357 			cci0_i2c1: i2c-bus@1 {
3358 				reg = <1>;
3360 				#address-cells = <1>;
3377 			pinctrl-1 = <&cci1_0_sleep &cci1_1_sleep>;
3380 			#address-cells = <1>;
3386 				#address-cells = <1>;
3390 			cci1_i2c1: i2c-bus@1 {
3391 				reg = <1>;
3393 				#address-cells = <1>;
3410 			pinctrl-1 = <&cci2_0_sleep &cci2_1_sleep>;
3413 			#address-cells = <1>;
3419 				#address-cells = <1>;
3423 			cci2_i2c1: i2c-bus@1 {
3424 				reg = <1>;
3426 				#address-cells = <1>;
3439 			#clock-cells = <1>;
3440 			#reset-cells = <1>;
3441 			#power-domain-cells = <1>;
3469 			#interrupt-cells = <1>;
3505 					#address-cells = <1>;
3516 					port@1 {
3517 						reg = <1>;
3581 							 <&mdss_dsi0_phy 1>;
3590 				#address-cells = <1>;
3596 					#address-cells = <1>;
3607 					port@1 {
3608 						reg = <1>;
3649 				#clock-cells = <1>;
3678 							 <&mdss_dsi1_phy 1>;
3687 				#address-cells = <1>;
3693 					#address-cells = <1>;
3704 					port@1 {
3705 						reg = <1>;
3727 				#clock-cells = <1>;
3795 					#address-cells = <1>;
3806 					port@1 {
3807 						reg = <1>;
3826 				 <&mdss_dsi0_phy 1>,
3828 				 <&mdss_dsi1_phy 1>,
3841 			#clock-cells = <1>;
3842 			#reset-cells = <1>;
3843 			#power-domain-cells = <1>;
3883 			#clock-cells = <1>;
3884 			#phy-cells = <1>;
3891 				#address-cells = <1>;
3901 				port@1 {
3902 					reg = <1>;
3990 					#address-cells = <1>;
4000 					port@1 {
4001 						reg = <1>;
4018 					  <125 63 1>, <126 716 12>,
4037 			#thermal-sensor-cells = <1>;
4052 			#thermal-sensor-cells = <1>;
4067 			#thermal-sensor-cells = <1>;
4101 			interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
4163 			cci0_1_default: cci0-1-default-state {
4179 			cci0_1_sleep: cci0-1-sleep-state {
4227 			cci1_1_default: cci1-1-default-state {
4243 			cci1_1_sleep: cci1-1-sleep-state {
4291 			cci2_1_default: cci2-1-default-state {
4307 			cci2_1_sleep: cci2-1-sleep-state {
4962 			#global-interrupts = <1>;
4977 			#redistributor-regions = <1>;
4989 				#msi-cells = <1>;
4998 			#address-cells = <1>;
4999 			#size-cells = <1>;
5016 				frame-number = <1>;
5079 				    "drv-1",
5105 				#clock-cells = <1>;
5113 				#power-domain-cells = <1>;
5197 					  "dcvsh-irq-1",
5204 			#freq-domain-cells = <1>;
5205 			#clock-cells = <1>;
5226 				opp-1 {
5278 				opp-1 {
5333 					      <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
5383 					#address-cells = <1>;
5438 					#address-cells = <1>;
5441 					q6apm: service@1 {
5450 							#sound-dai-cells = <1>;
5490 					      <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
5542 					#address-cells = <1>;
5545 					compute-cb@1 {
5547 						reg = <1>;
5681 			thermal-sensors = <&tsens0 1>;
6011 			thermal-sensors = <&tsens1 1>;
6347 			thermal-sensors = <&tsens2 1>;