dts/qcom/sm8550.dtsi

50 			clock-mult = <1>;
58 			clock-mult = <1>;
139 			clocks = <&cpufreq_hw 1>;
144 			qcom,freq-domain = <&cpufreq_hw 1>;
160 			clocks = <&cpufreq_hw 1>;
165 			qcom,freq-domain = <&cpufreq_hw 1>;
181 			clocks = <&cpufreq_hw 1>;
186 			qcom,freq-domain = <&cpufreq_hw 1>;
202 			clocks = <&cpufreq_hw 1>;
207 			qcom,freq-domain = <&cpufreq_hw 1>;
289 			BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
319 			CLUSTER_SLEEP_1: cluster-sleep-1 {
343 	mc_virt: interconnect-1 {
595 			qcom,client-id = <1>;
704 			#qcom,smem-state-cells = <1>;
728 			#qcom,smem-state-cells = <1>;
748 		qcom,remote-pid = <1>;
752 			#qcom,smem-state-cells = <1>;
763 			#qcom,smem-state-cells = <1>;
784 			#clock-cells = <1>;
785 			#reset-cells = <1>;
786 			#power-domain-cells = <1>;
792 				 <&ufs_mem_phy 1>,
850 				#address-cells = <1>;
857 				       <&gpi_dma2 1 0 QCOM_GPI_I2C>;
875 				       <&gpi_dma2 1 0 QCOM_GPI_SPI>;
877 				#address-cells = <1>;
890 				#address-cells = <1>;
896 				dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
897 				       <&gpi_dma2 1 1 QCOM_GPI_I2C>;
914 				dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
915 				       <&gpi_dma2 1 1 QCOM_GPI_SPI>;
917 				#address-cells = <1>;
930 				#address-cells = <1>;
937 				       <&gpi_dma2 1 2 QCOM_GPI_I2C>;
955 				       <&gpi_dma2 1 2 QCOM_GPI_SPI>;
957 				#address-cells = <1>;
970 				#address-cells = <1>;
977 				       <&gpi_dma2 1 3 QCOM_GPI_I2C>;
995 				       <&gpi_dma2 1 3 QCOM_GPI_I2C>;
997 				#address-cells = <1>;
1010 				#address-cells = <1>;
1017 				       <&gpi_dma2 1 4 QCOM_GPI_I2C>;
1035 				       <&gpi_dma2 1 4 QCOM_GPI_I2C>;
1037 				#address-cells = <1>;
1050 				#address-cells = <1>;
1057 				       <&gpi_dma2 1 5 QCOM_GPI_I2C>;
1075 				       <&gpi_dma2 1 5 QCOM_GPI_SPI>;
1077 				#address-cells = <1>;
1104 				#address-cells = <1>;
1111 				       <&gpi_dma2 1 7 QCOM_GPI_I2C>;
1129 				       <&gpi_dma2 1 7 QCOM_GPI_SPI>;
1131 				#address-cells = <1>;
1156 				#address-cells = <1>;
1173 				#address-cells = <1>;
1190 				#address-cells = <1>;
1207 				#address-cells = <1>;
1224 				#address-cells = <1>;
1241 				#address-cells = <1>;
1258 				#address-cells = <1>;
1275 				#address-cells = <1>;
1292 				#address-cells = <1>;
1309 				#address-cells = <1>;
1364 				#address-cells = <1>;
1371 				       <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1389 				       <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1391 				#address-cells = <1>;
1404 				#address-cells = <1>;
1410 				dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1411 				       <&gpi_dma1 1 1 QCOM_GPI_I2C>;
1428 				dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1429 				       <&gpi_dma1 1 1 QCOM_GPI_SPI>;
1431 				#address-cells = <1>;
1444 				#address-cells = <1>;
1451 				       <&gpi_dma1 1 2 QCOM_GPI_I2C>;
1469 				       <&gpi_dma1 1 2 QCOM_GPI_SPI>;
1471 				#address-cells = <1>;
1484 				#address-cells = <1>;
1491 				       <&gpi_dma1 1 3 QCOM_GPI_I2C>;
1509 				       <&gpi_dma1 1 3 QCOM_GPI_SPI>;
1511 				#address-cells = <1>;
1524 				#address-cells = <1>;
1531 				       <&gpi_dma1 1 4 QCOM_GPI_I2C>;
1549 				       <&gpi_dma1 1 4 QCOM_GPI_SPI>;
1551 				#address-cells = <1>;
1569 				       <&gpi_dma1 1 5 QCOM_GPI_I2C>;
1571 				#address-cells = <1>;
1589 				       <&gpi_dma1 1 5 QCOM_GPI_SPI>;
1591 				#address-cells = <1>;
1609 				       <&gpi_dma1 1 6 QCOM_GPI_I2C>;
1611 				#address-cells = <1>;
1629 				       <&gpi_dma1 1 6 QCOM_GPI_SPI>;
1631 				#address-cells = <1>;
1710 		pcie0: pcie@1c00000 {
1746 			#interrupt-cells = <1>;
1748 			interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1798 		pcie0_phy: phy@1c06000 {
1826 		pcie1: pcie@1c08000 {
1843 			linux,pci-domain = <1>;
1862 			#interrupt-cells = <1>;
1864 			interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1920 		pcie1_phy: phy@1c0e000 {
1941 			#clock-cells = <1>;
1949 		cryptobam: dma-controller@1dc4000 {
1953 			#dma-cells = <1>;
1960 		crypto: crypto@1dfa000 {
1971 		ufs_mem_phy: phy@1d80000 {
1986 			#clock-cells = <1>;
1992 		ufs_mem_hc: ufs@1d84000 {
2000 			#reset-cells = <1>;
2076 		ice: crypto@1d88000 {
2083 		tcsr_mutex: hwlock@1f40000 {
2086 			#hwlock-cells = <1>;
2089 		tcsr: clock-controller@1fc0000 {
2093 			#clock-cells = <1>;
2094 			#reset-cells = <1>;
2109 				 <&adreno_smmu 1 0x0>;
2226 			#clock-cells = <1>;
2227 			#reset-cells = <1>;
2228 			#power-domain-cells = <1>;
2236 			#global-interrupts = <1>;
2290 					      <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>;
2307 					   <&ipa_smp2p_out 1>;
2320 					      <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>,
2352 				qcom,remote-pid = <1>;
2367 			#sound-dai-cells = <1>;
2396 			#sound-dai-cells = <1>;
2411 			#sound-dai-cells = <1>;
2425 			qcom,din-ports = <1>;
2440 			#sound-dai-cells = <1>;
2455 			#sound-dai-cells = <1>;
2469 			#sound-dai-cells = <1>;
2498 			#sound-dai-cells = <1>;
2529 			#sound-dai-cells = <1>;
2543 			#sound-dai-cells = <1>;
2563 					slew-rate = <1>;
2571 					slew-rate = <1>;
2581 					slew-rate = <1>;
2589 					slew-rate = <1>;
2631 					slew-rate = <1>;
2639 					slew-rate = <1>;
2649 					slew-rate = <1>;
2657 					slew-rate = <1>;
2745 			#clock-cells = <1>;
2746 			#reset-cells = <1>;
2747 			#power-domain-cells = <1>;
2762 			pinctrl-1 = <&cci0_0_sleep &cci0_1_sleep>;
2765 			#address-cells = <1>;
2771 				#address-cells = <1>;
2775 			cci0_i2c1: i2c-bus@1 {
2776 				reg = <1>;
2778 				#address-cells = <1>;
2795 			pinctrl-1 = <&cci1_0_sleep>;
2798 			#address-cells = <1>;
2804 				#address-cells = <1>;
2821 			pinctrl-1 = <&cci2_0_sleep &cci2_1_sleep>;
2824 			#address-cells = <1>;
2830 				#address-cells = <1>;
2834 			cci2_i2c1: i2c-bus@1 {
2835 				reg = <1>;
2837 				#address-cells = <1>;
2851 			#clock-cells = <1>;
2852 			#reset-cells = <1>;
2853 			#power-domain-cells = <1>;
2863 			#interrupt-cells = <1>;
2916 					#address-cells = <1>;
2926 					port@1 {
2927 						reg = <1>;
3002 					#address-cells = <1>;
3012 					port@1 {
3013 						reg = <1>;
3071 							 <&mdss_dsi0_phy 1>;
3078 				#address-cells = <1>;
3084 					#address-cells = <1>;
3094 					port@1 {
3095 						reg = <1>;
3134 				#clock-cells = <1>;
3166 							 <&mdss_dsi1_phy 1>;
3173 				#address-cells = <1>;
3179 					#address-cells = <1>;
3189 					port@1 {
3190 						reg = <1>;
3210 				#clock-cells = <1>;
3225 				 <&mdss_dsi0_phy 1>,
3227 				 <&mdss_dsi1_phy 1>,
3238 			#clock-cells = <1>;
3239 			#reset-cells = <1>;
3240 			#power-domain-cells = <1>;
3272 			#clock-cells = <1>;
3273 			#phy-cells = <1>;
3280 				#address-cells = <1>;
3290 				port@1 {
3291 					reg = <1>;
3377 					#address-cells = <1>;
3387 					port@1 {
3388 						reg = <1>;
3402 					  <125 63 1>, <126 716 12>,
3417 			#thermal-sensor-cells = <1>;
3428 			#thermal-sensor-cells = <1>;
3439 			#thermal-sensor-cells = <1>;
3467 			interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
3520 			cci0_1_default: cci0-1-default-state {
3536 			cci0_1_sleep: cci0-1-sleep-state {
3616 			cci2_1_default: cci2-1-default-state {
3632 			cci2_1_sleep: cci2-1-sleep-state {
4173 			#global-interrupts = <1>;
4281 			#redistributor-regions = <1>;
4291 				#msi-cells = <1>;
4299 			#address-cells = <1>;
4300 			#size-cells = <1>;
4312 				frame-number = <1>;
4360 			reg-names = "drv-0", "drv-1", "drv-2", "drv-3";
4376 				#clock-cells = <1>;
4383 				#power-domain-cells = <1>;
4463 			interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2";
4464 			#freq-domain-cells = <1>;
4465 			#clock-cells = <1>;
4483 				opp-1 {
4532 				opp-1 {
4584 					      <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
4623 					#address-cells = <1>;
4672 					#address-cells = <1>;
4675 					q6apm: service@1 {
4690 							#sound-dai-cells = <1>;
4722 					      <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
4762 					#address-cells = <1>;
4765 					compute-cb@1 {
4767 						reg = <1>;
4863 			thermal-sensors = <&tsens0 1>;
5217 			thermal-sensors = <&tsens1 1>;
5637 			thermal-sensors = <&tsens2 1>;
5667 		gpuss-1-thermal {