Lines Matching +full:1 +full:c0e000
143 qcom,freq-domain = <&cpufreq_hw 1>;
145 clocks = <&cpufreq_hw 1>;
162 qcom,freq-domain = <&cpufreq_hw 1>;
164 clocks = <&cpufreq_hw 1>;
181 qcom,freq-domain = <&cpufreq_hw 1>;
183 clocks = <&cpufreq_hw 1>;
260 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
280 CLUSTER_SLEEP_1: cluster-sleep-1 {
295 #reset-cells = <1>;
305 mc_virt: interconnect-1 {
545 qcom,client-id = <1>;
648 #qcom,smem-state-cells = <1>;
672 #qcom,smem-state-cells = <1>;
692 qcom,remote-pid = <1>;
696 #qcom,smem-state-cells = <1>;
707 #qcom,smem-state-cells = <1>;
731 #qcom,smem-state-cells = <1>;
751 #clock-cells = <1>;
752 #reset-cells = <1>;
753 #power-domain-cells = <1>;
760 <&ufs_mem_phy 1>,
816 #address-cells = <1>;
823 <&gpi_dma2 1 0 QCOM_GPI_I2C>;
840 <&gpi_dma2 1 0 QCOM_GPI_SPI>;
842 #address-cells = <1>;
855 #address-cells = <1>;
861 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
862 <&gpi_dma2 1 1 QCOM_GPI_I2C>;
878 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
879 <&gpi_dma2 1 1 QCOM_GPI_SPI>;
881 #address-cells = <1>;
894 #address-cells = <1>;
901 <&gpi_dma2 1 2 QCOM_GPI_I2C>;
918 <&gpi_dma2 1 2 QCOM_GPI_SPI>;
920 #address-cells = <1>;
933 #address-cells = <1>;
940 <&gpi_dma2 1 3 QCOM_GPI_I2C>;
957 <&gpi_dma2 1 3 QCOM_GPI_I2C>;
959 #address-cells = <1>;
972 #address-cells = <1>;
979 <&gpi_dma2 1 4 QCOM_GPI_I2C>;
996 <&gpi_dma2 1 4 QCOM_GPI_I2C>;
998 #address-cells = <1>;
1011 #address-cells = <1>;
1018 <&gpi_dma2 1 5 QCOM_GPI_I2C>;
1052 <&gpi_dma2 1 5 QCOM_GPI_SPI>;
1054 #address-cells = <1>;
1067 #address-cells = <1>;
1074 <&gpi_dma2 1 6 QCOM_GPI_I2C>;
1091 <&gpi_dma2 1 6 QCOM_GPI_SPI>;
1093 #address-cells = <1>;
1143 #address-cells = <1>;
1150 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
1170 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
1172 #address-cells = <1>;
1185 #address-cells = <1>;
1191 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
1192 <&gpi_dma0 1 1 QCOM_GPI_I2C>;
1209 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1210 <&gpi_dma0 1 1 QCOM_GPI_SPI>;
1212 #address-cells = <1>;
1225 #address-cells = <1>;
1232 <&gpi_dma0 1 2 QCOM_GPI_I2C>;
1250 <&gpi_dma0 1 2 QCOM_GPI_SPI>;
1252 #address-cells = <1>;
1266 #address-cells = <1>;
1273 <&gpi_dma0 1 3 QCOM_GPI_I2C>;
1291 <&gpi_dma0 1 3 QCOM_GPI_SPI>;
1293 #address-cells = <1>;
1306 #address-cells = <1>;
1313 <&gpi_dma0 1 4 QCOM_GPI_I2C>;
1333 <&gpi_dma0 1 4 QCOM_GPI_SPI>;
1335 #address-cells = <1>;
1348 #address-cells = <1>;
1355 <&gpi_dma0 1 5 QCOM_GPI_I2C>;
1373 <&gpi_dma0 1 5 QCOM_GPI_SPI>;
1375 #address-cells = <1>;
1389 #address-cells = <1>;
1396 <&gpi_dma0 1 6 QCOM_GPI_I2C>;
1414 <&gpi_dma0 1 6 QCOM_GPI_SPI>;
1416 #address-cells = <1>;
1483 #address-cells = <1>;
1490 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1508 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1510 #address-cells = <1>;
1523 #address-cells = <1>;
1529 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1530 <&gpi_dma1 1 1 QCOM_GPI_I2C>;
1547 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1548 <&gpi_dma1 1 1 QCOM_GPI_SPI>;
1550 #address-cells = <1>;
1563 #address-cells = <1>;
1570 <&gpi_dma1 1 2 QCOM_GPI_I2C>;
1588 <&gpi_dma1 1 2 QCOM_GPI_SPI>;
1590 #address-cells = <1>;
1603 #address-cells = <1>;
1610 <&gpi_dma1 1 3 QCOM_GPI_I2C>;
1628 <&gpi_dma1 1 3 QCOM_GPI_SPI>;
1630 #address-cells = <1>;
1643 #address-cells = <1>;
1650 <&gpi_dma1 1 4 QCOM_GPI_I2C>;
1668 <&gpi_dma1 1 4 QCOM_GPI_SPI>;
1670 #address-cells = <1>;
1688 <&gpi_dma1 1 5 QCOM_GPI_I2C>;
1690 #address-cells = <1>;
1708 <&gpi_dma1 1 5 QCOM_GPI_SPI>;
1710 #address-cells = <1>;
1728 <&gpi_dma1 1 6 QCOM_GPI_I2C>;
1730 #address-cells = <1>;
1748 <&gpi_dma1 1 6 QCOM_GPI_SPI>;
1750 #address-cells = <1>;
1761 pcie0: pcie@1c00000 {
1772 num-lanes = <1>;
1799 #interrupt-cells = <1>;
1801 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1861 /* GEN 1 x1 */
1865 opp-peak-kBps = <250000 1>;
1872 opp-peak-kBps = <500000 1>;
1879 opp-peak-kBps = <984500 1>;
1894 pcie0_phy: phy@1c06000 {
1923 pcie1: pcie@1c08000 {
1932 linux,pci-domain = <1>;
1961 #interrupt-cells = <1>;
1963 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2021 /* GEN 1 x1 */
2025 opp-peak-kBps = <250000 1>;
2028 /* GEN 1 x2 and GEN 2 x1 */
2032 opp-peak-kBps = <500000 1>;
2039 opp-peak-kBps = <1000000 1>;
2046 opp-peak-kBps = <984500 1>;
2053 opp-peak-kBps = <1969000 1>;
2060 opp-peak-kBps = <3938000 1>;
2075 pcie1_phy: phy@1c0e000 {
2091 #clock-cells = <1>;
2152 tcsr_mutex: hwlock@1f40000 {
2155 #hwlock-cells = <1>;
2158 tcsr: syscon@1fc0000 {
2175 <&adreno_smmu 1 0x400>;
2311 #clock-cells = <1>;
2312 #reset-cells = <1>;
2313 #power-domain-cells = <1>;
2321 #global-interrupts = <1>;
2391 #clock-cells = <1>;
2392 #phy-cells = <1>;
2399 #address-cells = <1>;
2409 port@1 {
2410 reg = <1>;
2433 <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>,
2470 #address-cells = <1>;
2473 compute-cb@1 {
2475 reg = <1>;
2507 #sound-dai-cells = <1>;
2536 #sound-dai-cells = <1>;
2552 #sound-dai-cells = <1>;
2580 #sound-dai-cells = <1>;
2596 #sound-dai-cells = <1>;
2611 #sound-dai-cells = <1>;
2640 #sound-dai-cells = <1>;
2672 #sound-dai-cells = <1>;
2687 #sound-dai-cells = <1>;
2697 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
2734 #address-cells = <1>;
2737 q6apm: service@1 {
2751 #sound-dai-cells = <1>;
2773 #address-cells = <1>;
2803 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
2840 #address-cells = <1>;
2843 compute-cb@1 {
2845 reg = <1>;
2910 <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>,
2940 qcom,remote-pid = <1>;
2951 #clock-cells = <1>;
2952 #reset-cells = <1>;
2953 #power-domain-cells = <1>;
2973 pinctrl-1 = <&cci0_sleep &cci1_sleep>;
2977 #address-cells = <1>;
2983 #address-cells = <1>;
2987 cci0_i2c1: i2c-bus@1 {
2988 reg = <1>;
2990 #address-cells = <1>;
3012 pinctrl-1 = <&cci2_sleep &cci3_sleep>;
3016 #address-cells = <1>;
3022 #address-cells = <1>;
3026 cci1_i2c1: i2c-bus@1 {
3027 reg = <1>;
3029 #address-cells = <1>;
3043 #clock-cells = <1>;
3044 #reset-cells = <1>;
3045 #power-domain-cells = <1>;
3074 #interrupt-cells = <1>;
3113 #address-cells = <1>;
3123 port@1 {
3124 reg = <1>;
3204 #address-cells = <1>;
3214 port@1 {
3215 reg = <1>;
3270 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
3278 #address-cells = <1>;
3284 #address-cells = <1>;
3294 port@1 {
3295 reg = <1>;
3330 #clock-cells = <1>;
3362 assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>;
3370 #address-cells = <1>;
3376 #address-cells = <1>;
3386 port@1 {
3387 reg = <1>;
3403 #clock-cells = <1>;
3422 <&mdss_dsi0_phy 1>,
3424 <&mdss_dsi1_phy 1>,
3435 #clock-cells = <1>;
3436 #reset-cells = <1>;
3437 #power-domain-cells = <1>;
3445 <94 609 31>, <125 63 1>, <126 716 12>;
3459 #thermal-sensor-cells = <1>;
3470 #thermal-sensor-cells = <1>;
3501 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
4046 slew-rate = <1>;
4054 slew-rate = <1>;
4064 slew-rate = <1>;
4072 slew-rate = <1>;
4112 slew-rate = <1>;
4120 slew-rate = <1>;
4130 slew-rate = <1>;
4138 slew-rate = <1>;
4149 #address-cells = <1>;
4150 #size-cells = <1>;
4162 #global-interrupts = <1>;
4266 #redistributor-regions = <1>;
4279 #msi-cells = <1>;
4285 #address-cells = <1>;
4286 #size-cells = <1>;
4300 frame-number = <1>;
4349 reg-names = "drv-0", "drv-1", "drv-2", "drv-3";
4365 #clock-cells = <1>;
4372 #power-domain-cells = <1>;
4448 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2";
4449 #freq-domain-cells = <1>;
4450 #clock-cells = <1>;
4471 ufs_mem_hc: ufshc@1d84000 {
4479 #reset-cells = <1>;
4523 ufs_mem_phy: phy@1d87000 {
4537 #clock-cells = <1>;
4543 ice: crypto@1d88000 {
4550 cryptobam: dma-controller@1dc4000 {
4554 #dma-cells = <1>;
4564 crypto: crypto@1dfa000 {
4675 #address-cells = <1>;
4685 port@1 {
4686 reg = <1>;
4734 thermal-sensors = <&tsens0 1>;
5106 thermal-sensors = <&tsens1 1>;