Lines Matching +full:1 +full:c0e000
139 clocks = <&cpufreq_hw 1>;
142 qcom,freq-domain = <&cpufreq_hw 1>;
158 clocks = <&cpufreq_hw 1>;
161 qcom,freq-domain = <&cpufreq_hw 1>;
177 clocks = <&cpufreq_hw 1>;
180 qcom,freq-domain = <&cpufreq_hw 1>;
260 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
280 CLUSTER_SLEEP_AOSS_SLEEP: cluster-sleep-1 {
294 #reset-cells = <1>;
518 qcom,client-id = <1>;
567 #qcom,smem-state-cells = <1>;
591 #qcom,smem-state-cells = <1>;
611 qcom,remote-pid = <1>;
615 #qcom,smem-state-cells = <1>;
626 #qcom,smem-state-cells = <1>;
650 #qcom,smem-state-cells = <1>;
670 #clock-cells = <1>;
671 #reset-cells = <1>;
672 #power-domain-cells = <1>;
693 <&ufs_mem_phy 1>,
751 <&gpi_dma2 1 0 QCOM_GPI_I2C>;
753 #address-cells = <1>;
767 <&gpi_dma2 1 0 QCOM_GPI_SPI>;
769 #address-cells = <1>;
782 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
783 <&gpi_dma2 1 1 QCOM_GPI_I2C>;
785 #address-cells = <1>;
798 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
799 <&gpi_dma2 1 1 QCOM_GPI_SPI>;
801 #address-cells = <1>;
815 <&gpi_dma2 1 2 QCOM_GPI_I2C>;
817 #address-cells = <1>;
831 <&gpi_dma2 1 2 QCOM_GPI_SPI>;
833 #address-cells = <1>;
847 <&gpi_dma2 1 3 QCOM_GPI_I2C>;
849 #address-cells = <1>;
863 <&gpi_dma2 1 3 QCOM_GPI_SPI>;
865 #address-cells = <1>;
881 <&gpi_dma2 1 4 QCOM_GPI_SPI>;
883 #address-cells = <1>;
910 <&gpi_dma2 1 5 QCOM_GPI_I2C>;
912 #address-cells = <1>;
926 <&gpi_dma2 1 5 QCOM_GPI_SPI>;
928 #address-cells = <1>;
977 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
979 #address-cells = <1>;
993 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
995 #address-cells = <1>;
1008 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
1009 <&gpi_dma0 1 1 QCOM_GPI_I2C>;
1011 #address-cells = <1>;
1024 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1025 <&gpi_dma0 1 1 QCOM_GPI_SPI>;
1027 #address-cells = <1>;
1041 <&gpi_dma0 1 2 QCOM_GPI_I2C>;
1043 #address-cells = <1>;
1057 <&gpi_dma0 1 2 QCOM_GPI_SPI>;
1059 #address-cells = <1>;
1088 <&gpi_dma0 1 3 QCOM_GPI_SPI>;
1090 #address-cells = <1>;
1104 <&gpi_dma0 1 4 QCOM_GPI_I2C>;
1106 #address-cells = <1>;
1120 <&gpi_dma0 1 4 QCOM_GPI_SPI>;
1122 #address-cells = <1>;
1136 <&gpi_dma0 1 5 QCOM_GPI_I2C>;
1138 #address-cells = <1>;
1152 <&gpi_dma0 1 5 QCOM_GPI_SPI>;
1154 #address-cells = <1>;
1168 <&gpi_dma0 1 6 QCOM_GPI_I2C>;
1170 #address-cells = <1>;
1184 <&gpi_dma0 1 6 QCOM_GPI_SPI>;
1186 #address-cells = <1>;
1213 <&gpi_dma0 1 7 QCOM_GPI_I2C>;
1215 #address-cells = <1>;
1229 <&gpi_dma0 1 7 QCOM_GPI_SPI>;
1231 #address-cells = <1>;
1280 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1282 #address-cells = <1>;
1296 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1298 #address-cells = <1>;
1311 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1312 <&gpi_dma1 1 1 QCOM_GPI_I2C>;
1314 #address-cells = <1>;
1327 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1328 <&gpi_dma1 1 1 QCOM_GPI_SPI>;
1330 #address-cells = <1>;
1344 <&gpi_dma1 1 2 QCOM_GPI_I2C>;
1346 #address-cells = <1>;
1360 <&gpi_dma1 1 2 QCOM_GPI_SPI>;
1362 #address-cells = <1>;
1376 <&gpi_dma1 1 3 QCOM_GPI_I2C>;
1378 #address-cells = <1>;
1392 <&gpi_dma1 1 3 QCOM_GPI_SPI>;
1394 #address-cells = <1>;
1408 <&gpi_dma1 1 4 QCOM_GPI_I2C>;
1410 #address-cells = <1>;
1424 <&gpi_dma1 1 4 QCOM_GPI_SPI>;
1426 #address-cells = <1>;
1440 <&gpi_dma1 1 5 QCOM_GPI_I2C>;
1442 #address-cells = <1>;
1456 <&gpi_dma1 1 5 QCOM_GPI_SPI>;
1458 #address-cells = <1>;
1513 pcie0: pcie@1c00000 {
1524 num-lanes = <1>;
1548 #interrupt-cells = <1>;
1550 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1598 pcie0_phy: phy@1c06000 {
1622 pcie1: pcie@1c08000 {
1631 linux,pci-domain = <1>;
1657 #interrupt-cells = <1>;
1659 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1705 pcie1_phy: phy@1c0e000 {
1729 ufs_mem_hc: ufshc@1d84000 {
1737 #reset-cells = <1>;
1781 ufs_mem_phy: phy@1d87000 {
1797 #clock-cells = <1>;
1803 cryptobam: dma-controller@1dc4000 {
1807 #dma-cells = <1>;
1816 crypto: crypto@1dfa000 {
1829 ipa: ipa@1e40000 {
1844 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>;
1861 <&ipa_smp2p_out 1>;
1868 tcsr_mutex: hwlock@1f40000 {
1871 #hwlock-cells = <1>;
1874 tcsr: syscon@1fc0000 {
1905 iommus = <&adreno_smmu 0 0x400>, <&adreno_smmu 1 0x400>;
2029 #clock-cells = <1>;
2030 #reset-cells = <1>;
2031 #power-domain-cells = <1>;
2085 <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>,
2117 qcom,remote-pid = <1>;
2127 <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>,
2164 #address-cells = <1>;
2167 compute-cb@1 {
2169 reg = <1>;
2274 #clock-cells = <1>;
2275 #phy-cells = <1>;
2282 #address-cells = <1>;
2292 port@1 {
2293 reg = <1>;
2416 #address-cells = <1>;
2426 port@1 {
2427 reg = <1>;
2517 #interrupt-cells = <1>;
2585 #address-cells = <1>;
2595 port@1 {
2596 reg = <1>;
2647 #address-cells = <1>;
2657 port@1 {
2658 reg = <1>;
2715 <&mdss_dsi0_phy 1>;
2723 #address-cells = <1>;
2753 #address-cells = <1>;
2763 port@1 {
2764 reg = <1>;
2780 #clock-cells = <1>;
2814 <&mdss_dsi1_phy 1>;
2822 #address-cells = <1>;
2852 #address-cells = <1>;
2862 port@1 {
2863 reg = <1>;
2879 #clock-cells = <1>;
2894 <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>,
2895 <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>,
2905 #clock-cells = <1>;
2906 #reset-cells = <1>;
2907 #power-domain-cells = <1>;
2915 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, <55 306 4>,
2917 <69 86 1>, <70 520 54>, <124 609 31>, <155 63 1>,
2932 #thermal-sensor-cells = <1>;
2943 #thermal-sensor-cells = <1>;
2970 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
3293 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
3329 #address-cells = <1>;
3345 #address-cells = <1>;
3347 #sound-dai-cells = <1>;
3363 #address-cells = <1>;
3365 #sound-dai-cells = <1>;
3372 dai@1 {
3373 reg = <1>;
3399 #address-cells = <1>;
3427 #redistributor-regions = <1>;
3436 #address-cells = <1>;
3437 #size-cells = <1>;
3451 frame-number = <1>;
3499 reg-names = "drv-0", "drv-1", "drv-2";
3511 #clock-cells = <1>;
3518 #power-domain-cells = <1>;
3582 "dcvsh-irq-1",
3588 #freq-domain-cells = <1>;
3589 #clock-cells = <1>;
3598 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
3637 #address-cells = <1>;
3640 compute-cb@1 {
3642 reg = <1>;
3706 thermal-sensors = <&tsens0 1>;
4288 thermal-sensors = <&tsens1 1>;