dts/qcom/sdm845-wcd9340.dtsi

1 // SPDX-License-Identifier: GPL-2.0
13 		#address-cells = <2>;
14 		#size-cells = <0>;
24 			slim-ifc-dev = <&wcd9340_ifd>;
26 			#sound-dai-cells = <1>;
28 			interrupts-extended = <&tlmm 54 IRQ_TYPE_LEVEL_HIGH>;
29 			interrupt-controller;
30 			#interrupt-cells = <1>;
32 			clock-names = "extclk";
35 			#clock-cells = <0>;
36 			clock-frequency = <9600000>;
37 			clock-output-names = "mclk";
39 			pinctrl-0 = <&wcd_intr_default>;
40 			pinctrl-names = "default";
42 			qcom,micbias1-microvolt = <1800000>;
43 			qcom,micbias2-microvolt = <1800000>;
44 			qcom,micbias3-microvolt = <1800000>;
45 			qcom,micbias4-microvolt = <1800000>;
47 			#address-cells = <1>;
48 			#size-cells = <1>;
50 			wcdgpio: gpio-controller@42 {
51 				compatible = "qcom,wcd9340-gpio";
52 				gpio-controller;
53 				#gpio-cells = <2>;
58 				compatible = "qcom,soundwire-v1.3.0";
60 				interrupts-extended = <&wcd9340 20>;
62 				qcom,dout-ports = <6>;
63 				qcom,din-ports = <2>;
64 				qcom,ports-sinterval-low = /bits/ 8  <0x07 0x1f 0x3f 0x7 0x1f 0x3f 0x0f 0x0f>;
65 				qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x6 0x12 0x0d 0x07 0x0a>;
66 				qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x1f 0x00 0x00 0x1f 0x00 0x00>;
68 				#sound-dai-cells = <1>;
70 				clock-names = "iface";
71 				#address-cells = <2>;
72 				#size-cells = <0>;
79 	wcd_intr_default: wcd-intr-default-state {
83 		bias-pull-down;
84 		drive-strength = <2>;