dts/qcom/sc8280xp.dtsi

4096 				 <&dispcc0 DISP_CC_MDSS_AHB_CLK>,
4097 				 <&dispcc0 DISP_CC_MDSS_MDP_CLK>;
4106 			power-domains = <&dispcc0 MDSS_GDSC>;
4107 			resets = <&dispcc0 DISP_CC_MDSS_CORE_BCR>;
4125 					 <&dispcc0 DISP_CC_MDSS_AHB_CLK>,
4126 					 <&dispcc0 DISP_CC_MDSS_MDP_LUT_CLK>,
4127 					 <&dispcc0 DISP_CC_MDSS_MDP_CLK>,
4128 					 <&dispcc0 DISP_CC_MDSS_VSYNC_CLK>;
4139 				assigned-clocks = <&dispcc0 DISP_CC_MDSS_VSYNC_CLK>;
4214 				clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>,
4215 					 <&dispcc0 DISP_CC_MDSS_DPTX0_AUX_CLK>,
4216 					 <&dispcc0 DISP_CC_MDSS_DPTX0_LINK_CLK>,
4217 					 <&dispcc0 DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
4218 					 <&dispcc0 DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
4224 				assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
4225 						  <&dispcc0 DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
4293 				clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>,
4294 					 <&dispcc0 DISP_CC_MDSS_DPTX1_AUX_CLK>,
4295 					 <&dispcc0 DISP_CC_MDSS_DPTX1_LINK_CLK>,
4296 					 <&dispcc0 DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>,
4297 					 <&dispcc0 DISP_CC_MDSS_DPTX1_PIXEL0_CLK>;
4302 				assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>,
4303 						  <&dispcc0 DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>;
4370 				clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>,
4371 					 <&dispcc0 DISP_CC_MDSS_DPTX2_AUX_CLK>,
4372 					 <&dispcc0 DISP_CC_MDSS_DPTX2_LINK_CLK>,
4373 					 <&dispcc0 DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>,
4374 					 <&dispcc0 DISP_CC_MDSS_DPTX2_PIXEL0_CLK>;
4384 				assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>,
4385 						  <&dispcc0 DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>;
4442 				clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>,
4443 					 <&dispcc0 DISP_CC_MDSS_DPTX3_AUX_CLK>,
4444 					 <&dispcc0 DISP_CC_MDSS_DPTX3_LINK_CLK>,
4445 					 <&dispcc0 DISP_CC_MDSS_DPTX3_LINK_INTF_CLK>,
4446 					 <&dispcc0 DISP_CC_MDSS_DPTX3_PIXEL0_CLK>;
4456 				assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX3_LINK_CLK_SRC>,
4457 						  <&dispcc0 DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC>;
4514 			clocks = <&dispcc0 DISP_CC_MDSS_DPTX2_AUX_CLK>,
4515 				 <&dispcc0 DISP_CC_MDSS_AHB_CLK>;
4532 			clocks = <&dispcc0 DISP_CC_MDSS_DPTX3_AUX_CLK>,
4533 				 <&dispcc0 DISP_CC_MDSS_AHB_CLK>;
4543 		dispcc0: clock-controller@af00000 {  label
4544 			compatible = "qcom,sc8280xp-dispcc0";