Lines Matching +full:1 +full:c18000
148 clocks = <&cpufreq_hw 1>;
155 qcom,freq-domain = <&cpufreq_hw 1>;
171 clocks = <&cpufreq_hw 1>;
178 qcom,freq-domain = <&cpufreq_hw 1>;
194 clocks = <&cpufreq_hw 1>;
201 qcom,freq-domain = <&cpufreq_hw 1>;
217 clocks = <&cpufreq_hw 1>;
224 qcom,freq-domain = <&cpufreq_hw 1>;
285 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
728 #qcom,smem-state-cells = <1>;
752 #qcom,smem-state-cells = <1>;
776 #qcom,smem-state-cells = <1>;
826 #clock-cells = <1>;
827 #reset-cells = <1>;
828 #power-domain-cells = <1>;
877 #address-cells = <1>;
878 #size-cells = <1>;
903 #address-cells = <1>;
919 #address-cells = <1>;
935 #address-cells = <1>;
951 #address-cells = <1>;
981 #address-cells = <1>;
997 #address-cells = <1>;
1013 #address-cells = <1>;
1029 #address-cells = <1>;
1045 #address-cells = <1>;
1061 #address-cells = <1>;
1080 #address-cells = <1>;
1093 #address-cells = <1>;
1109 #address-cells = <1>;
1125 #address-cells = <1>;
1141 #address-cells = <1>;
1157 #address-cells = <1>;
1188 #address-cells = <1>;
1204 #address-cells = <1>;
1220 #address-cells = <1>;
1236 #address-cells = <1>;
1252 #address-cells = <1>;
1268 #address-cells = <1>;
1298 #address-cells = <1>;
1314 #address-cells = <1>;
1333 #address-cells = <1>;
1346 #address-cells = <1>;
1362 #address-cells = <1>;
1378 #address-cells = <1>;
1394 #address-cells = <1>;
1410 #address-cells = <1>;
1426 #address-cells = <1>;
1442 #address-cells = <1>;
1473 #address-cells = <1>;
1489 #address-cells = <1>;
1505 #address-cells = <1>;
1521 #address-cells = <1>;
1537 #address-cells = <1>;
1553 #address-cells = <1>;
1569 #address-cells = <1>;
1585 #address-cells = <1>;
1601 #address-cells = <1>;
1617 #address-cells = <1>;
1633 #address-cells = <1>;
1649 #address-cells = <1>;
1665 #address-cells = <1>;
1681 #address-cells = <1>;
1697 #address-cells = <1>;
1713 #address-cells = <1>;
1734 pcie4: pcie@1c00000 {
1753 num-lanes = <1>;
1763 #interrupt-cells = <1>;
1765 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
1818 pcie4_phy: phy@1c06000 {
1847 pcie3b: pcie@1c08000 {
1876 #interrupt-cells = <1>;
1878 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 526 IRQ_TYPE_LEVEL_HIGH>,
1929 pcie3b_phy: phy@1c0e000 {
1958 pcie3a: pcie@1c10000 {
1987 #interrupt-cells = <1>;
1989 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH>,
2040 pcie3a_phy: phy@1c14000 {
2062 qcom,4ln-config-sel = <&tcsr 0xa044 1>;
2072 pcie2b: pcie@1c18000 {
2101 #interrupt-cells = <1>;
2103 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,
2154 pcie2b_phy: phy@1c1e000 {
2183 pcie2a: pcie@1c20000 {
2212 #interrupt-cells = <1>;
2214 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>,
2265 pcie2a_phy: phy@1c24000 {
2297 ufs_mem_hc: ufs@1d84000 {
2305 #reset-cells = <1>;
2342 ufs_mem_phy: phy@1d87000 {
2363 ufs_card_hc: ufs@1da4000 {
2371 #reset-cells = <1>;
2407 ufs_card_phy: phy@1da7000 {
2428 tcsr_mutex: hwlock@1f40000 {
2431 #hwlock-cells = <1>;
2434 tcsr: syscon@1fc0000 {
2449 iommus = <&gpu_smmu 0 0xc00>, <&gpu_smmu 1 0xc00>;
2568 #clock-cells = <1>;
2569 #reset-cells = <1>;
2570 #power-domain-cells = <1>;
2732 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
2770 #address-cells = <1>;
2773 q6apm: service@1 {
2786 #sound-dai-cells = <1>;
2819 #sound-dai-cells = <1>;
2850 #sound-dai-cells = <1>;
2875 #sound-dai-cells = <1>;
2895 #sound-dai-cells = <1>;
2926 #sound-dai-cells = <1>;
2936 #clock-cells = <1>;
2937 #reset-cells = <1>;
2952 #sound-dai-cells = <1>;
2984 #sound-dai-cells = <1>;
3008 slew-rate = <1>;
3016 slew-rate = <1>;
3026 slew-rate = <1>;
3034 slew-rate = <1>;
3112 slew-rate = <1>;
3120 slew-rate = <1>;
3130 slew-rate = <1>;
3138 slew-rate = <1>;
3147 #clock-cells = <1>;
3148 #reset-cells = <1>;
3210 #clock-cells = <1>;
3211 #phy-cells = <1>;
3216 #address-cells = <1>;
3225 port@1 {
3226 reg = <1>;
3271 #clock-cells = <1>;
3272 #phy-cells = <1>;
3277 #address-cells = <1>;
3286 port@1 {
3287 reg = <1>;
3314 #clock-cells = <1>;
3332 #clock-cells = <1>;
3354 opp-1 {
3408 opp-1 {
3517 "usb2-1", "usb3-1",
3580 #address-cells = <1>;
3590 port@1 {
3591 reg = <1>;
3657 #address-cells = <1>;
3667 port@1 {
3668 reg = <1>;
3696 pinctrl-1 = <&cci0_sleep>;
3699 #address-cells = <1>;
3707 #address-cells = <1>;
3711 cci0_i2c1: i2c-bus@1 {
3712 reg = <1>;
3714 #address-cells = <1>;
3737 pinctrl-1 = <&cci1_sleep>;
3740 #address-cells = <1>;
3748 #address-cells = <1>;
3752 cci1_i2c1: i2c-bus@1 {
3753 reg = <1>;
3755 #address-cells = <1>;
3777 pinctrl-1 = <&cci2_sleep>;
3780 #address-cells = <1>;
3788 #address-cells = <1>;
3792 cci2_i2c1: i2c-bus@1 {
3793 reg = <1>;
3795 #address-cells = <1>;
3818 pinctrl-1 = <&cci3_sleep>;
3821 #address-cells = <1>;
3829 #address-cells = <1>;
3833 cci3_i2c1: i2c-bus@1 {
3834 reg = <1>;
3836 #address-cells = <1>;
4047 #address-cells = <1>;
4052 #address-cells = <1>;
4056 port@1 {
4057 reg = <1>;
4058 #address-cells = <1>;
4064 #address-cells = <1>;
4070 #address-cells = <1>;
4085 #clock-cells = <1>;
4086 #reset-cells = <1>;
4087 #power-domain-cells = <1>;
4110 #interrupt-cells = <1>;
4144 #address-cells = <1>;
4240 #address-cells = <1>;
4251 port@1 {
4252 reg = <1>;
4318 #address-cells = <1>;
4329 port@1 {
4330 reg = <1>;
4386 assigned-clock-parents = <&mdss0_dp2_phy 0>, <&mdss0_dp2_phy 1>;
4394 #address-cells = <1>;
4404 port@1 {
4405 reg = <1>;
4458 assigned-clock-parents = <&mdss0_dp3_phy 0>, <&mdss0_dp3_phy 1>;
4466 #address-cells = <1>;
4476 port@1 {
4477 reg = <1>;
4519 #clock-cells = <1>;
4537 #clock-cells = <1>;
4555 <&mdss0_dp2_phy 1>,
4557 <&mdss0_dp3_phy 1>,
4564 #clock-cells = <1>;
4565 #power-domain-cells = <1>;
4566 #reset-cells = <1>;
4576 <54 263 1>,
4582 <69 86 1>,
4585 <159 638 1>,
4587 <168 801 1>,
4590 <201 449 1>,
4591 <202 89 1>,
4592 <203 451 1>,
4593 <204 462 1>,
4594 <205 264 1>,
4595 <206 579 1>,
4596 <207 653 1>,
4597 <208 656 1>,
4598 <209 659 1>,
4599 <210 122 1>,
4600 <211 699 1>,
4601 <212 705 1>,
4602 <213 450 1>,
4603 <214 643 1>,
4608 <232 269 1>,
4609 <233 377 1>,
4610 <234 372 1>,
4611 <235 138 1>,
4612 <236 857 1>,
4613 <237 860 1>,
4614 <238 137 1>,
4615 <239 668 1>,
4616 <240 366 1>,
4617 <241 949 1>,
4619 <247 769 1>,
4620 <248 768 1>,
4621 <249 663 1>,
4623 <252 798 1>,
4624 <253 765 1>,
4625 <254 763 1>,
4626 <255 454 1>,
4627 <258 139 1>,
4644 #thermal-sensor-cells = <1>;
4655 #thermal-sensor-cells = <1>;
4666 #thermal-sensor-cells = <1>;
4684 #thermal-sensor-cells = <1>;
4711 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
5020 #redistributor-regions = <1>;
5031 #msi-cells = <1>;
5045 #address-cells = <1>;
5046 #size-cells = <1>;
5058 frame-number = <1>;
5105 reg-names = "drv-0", "drv-1", "drv-2";
5112 <WAKE_TCS 3>, <CONTROL_TCS 1>;
5122 #clock-cells = <1>;
5129 #power-domain-cells = <1>;
5185 #interconnect-cells = <1>;
5197 "dcvsh-irq-1";
5202 #freq-domain-cells = <1>;
5203 #clock-cells = <1>;
5206 remoteproc_nsp0: remoteproc@1b300000 {
5212 <&smp2p_nsp0_in 1 IRQ_TYPE_EDGE_RISING>,
5247 #address-cells = <1>;
5250 compute-cb@1 {
5252 reg = <1>;
5343 <&smp2p_nsp1_in 1 IRQ_TYPE_EDGE_RISING>,
5397 #interrupt-cells = <1>;
5431 #address-cells = <1>;
5516 assigned-clock-parents = <&mdss1_dp0_phy 0>, <&mdss1_dp0_phy 1>;
5524 #address-cells = <1>;
5534 port@1 {
5535 reg = <1>;
5588 assigned-clock-parents = <&mdss1_dp1_phy 0>, <&mdss1_dp1_phy 1>;
5596 #address-cells = <1>;
5606 port@1 {
5607 reg = <1>;
5660 assigned-clock-parents = <&mdss1_dp2_phy 0>, <&mdss1_dp2_phy 1>;
5668 #address-cells = <1>;
5678 port@1 {
5679 reg = <1>;
5732 assigned-clock-parents = <&mdss1_dp3_phy 0>, <&mdss1_dp3_phy 1>;
5740 #address-cells = <1>;
5750 port@1 {
5751 reg = <1>;
5793 #clock-cells = <1>;
5811 #clock-cells = <1>;
5825 <&mdss1_dp0_phy 1>,
5827 <&mdss1_dp1_phy 1>,
5829 <&mdss1_dp2_phy 1>,
5831 <&mdss1_dp3_phy 1>,
5838 #clock-cells = <1>;
5839 #power-domain-cells = <1>;
5840 #reset-cells = <1>;
5883 thermal-sensors = <&tsens0 1>;