Lines Matching full:gcc
8 #include <dt-bindings/clock/qcom,gcc-sc8180x.h>
782 gcc: clock-controller@100000 { label
783 compatible = "qcom,gcc-sc8180x";
800 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
801 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
812 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
827 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
841 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
853 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
868 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
882 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
894 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
909 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
923 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
935 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
950 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
964 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
976 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
991 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1005 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1017 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1032 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1046 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1058 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1073 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1087 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1099 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1114 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1128 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1141 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1142 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1153 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1168 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1182 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1194 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1209 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1223 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1235 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1250 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1264 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1276 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1291 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1305 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1317 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1332 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1346 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1358 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1373 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1387 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1400 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
1401 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
1412 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
1427 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
1441 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
1453 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
1468 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
1482 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
1494 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
1509 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
1523 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
1535 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1550 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1564 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1576 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1591 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1605 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1617 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1632 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1646 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1744 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
1745 <&gcc GCC_PCIE_0_AUX_CLK>,
1746 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1747 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
1748 <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
1749 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
1750 <&gcc GCC_PCIE_0_CLKREF_CLK>,
1751 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
1761 assigned-clocks = <&gcc GCC_PCIE_0_AUX_CLK>;
1767 resets = <&gcc GCC_PCIE_0_BCR>;
1770 power-domains = <&gcc PCIE_0_GDSC>;
1796 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
1797 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1798 <&gcc GCC_PCIE_0_CLKREF_CLK>,
1799 <&gcc GCC_PCIE0_PHY_REFGEN_CLK>,
1800 <&gcc GCC_PCIE_0_PIPE_CLK>;
1810 resets = <&gcc GCC_PCIE_0_PHY_BCR>;
1813 assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>;
1865 clocks = <&gcc GCC_PCIE_3_PIPE_CLK>,
1866 <&gcc GCC_PCIE_3_AUX_CLK>,
1867 <&gcc GCC_PCIE_3_CFG_AHB_CLK>,
1868 <&gcc GCC_PCIE_3_MSTR_AXI_CLK>,
1869 <&gcc GCC_PCIE_3_SLV_AXI_CLK>,
1870 <&gcc GCC_PCIE_3_SLV_Q2A_AXI_CLK>,
1871 <&gcc GCC_PCIE_3_CLKREF_CLK>,
1872 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
1882 assigned-clocks = <&gcc GCC_PCIE_3_AUX_CLK>;
1888 resets = <&gcc GCC_PCIE_3_BCR>;
1891 power-domains = <&gcc PCIE_3_GDSC>;
1917 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
1918 <&gcc GCC_PCIE_3_CFG_AHB_CLK>,
1919 <&gcc GCC_PCIE_3_CLKREF_CLK>,
1920 <&gcc GCC_PCIE3_PHY_REFGEN_CLK>,
1921 <&gcc GCC_PCIE_3_PIPE_CLK>;
1932 resets = <&gcc GCC_PCIE_3_PHY_BCR>;
1935 assigned-clocks = <&gcc GCC_PCIE3_PHY_REFGEN_CLK>;
1987 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
1988 <&gcc GCC_PCIE_1_AUX_CLK>,
1989 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1990 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
1991 <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
1992 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
1993 <&gcc GCC_PCIE_1_CLKREF_CLK>,
1994 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
2004 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
2010 resets = <&gcc GCC_PCIE_1_BCR>;
2013 power-domains = <&gcc PCIE_1_GDSC>;
2039 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
2040 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
2041 <&gcc GCC_PCIE_1_CLKREF_CLK>,
2042 <&gcc GCC_PCIE1_PHY_REFGEN_CLK>,
2043 <&gcc GCC_PCIE_1_PIPE_CLK>;
2054 resets = <&gcc GCC_PCIE_1_PHY_BCR>;
2057 assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
2109 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>,
2110 <&gcc GCC_PCIE_2_AUX_CLK>,
2111 <&gcc GCC_PCIE_2_CFG_AHB_CLK>,
2112 <&gcc GCC_PCIE_2_MSTR_AXI_CLK>,
2113 <&gcc GCC_PCIE_2_SLV_AXI_CLK>,
2114 <&gcc GCC_PCIE_2_SLV_Q2A_AXI_CLK>,
2115 <&gcc GCC_PCIE_2_CLKREF_CLK>,
2116 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
2126 assigned-clocks = <&gcc GCC_PCIE_2_AUX_CLK>;
2132 resets = <&gcc GCC_PCIE_2_BCR>;
2135 power-domains = <&gcc PCIE_2_GDSC>;
2161 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
2162 <&gcc GCC_PCIE_2_CFG_AHB_CLK>,
2163 <&gcc GCC_PCIE_2_CLKREF_CLK>,
2164 <&gcc GCC_PCIE2_PHY_REFGEN_CLK>,
2165 <&gcc GCC_PCIE_2_PIPE_CLK>;
2176 resets = <&gcc GCC_PCIE_2_PHY_BCR>;
2179 assigned-clocks = <&gcc GCC_PCIE2_PHY_REFGEN_CLK>;
2194 resets = <&gcc GCC_UFS_PHY_BCR>;
2199 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
2200 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
2201 <&gcc GCC_UFS_PHY_AHB_CLK>,
2202 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
2204 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
2205 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
2206 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
2224 power-domains = <&gcc UFS_PHY_GDSC>;
2240 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
2241 <&gcc GCC_UFS_MEM_CLKREF_EN>;
2249 power-domains = <&gcc UFS_PHY_GDSC>;
2339 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
2340 <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
2370 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
2371 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
2396 <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
2397 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>;
2490 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
2503 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
2519 resets = <&gcc GCC_QUSB2PHY_MP0_BCR>;
2533 resets = <&gcc GCC_QUSB2PHY_MP1_BCR>;
2542 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
2543 <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
2544 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
2545 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
2551 resets = <&gcc GCC_USB3_DP_PHY_PRIM_SP0_BCR>,
2552 <&gcc GCC_USB3_PHY_PRIM_SP0_BCR>;
2590 clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>,
2591 <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
2592 <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>,
2593 <&gcc GCC_USB3_MP_PHY_PIPE_0_CLK>;
2599 resets = <&gcc GCC_USB3_UNIPHY_MP0_BCR>,
2600 <&gcc GCC_USB3UNIPHY_PHY_MP0_BCR>;
2603 power-domains = <&gcc USB30_MP_GDSC>;
2617 clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>,
2618 <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
2619 <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>,
2620 <&gcc GCC_USB3_MP_PHY_PIPE_1_CLK>;
2626 resets = <&gcc GCC_USB3_UNIPHY_MP1_BCR>,
2627 <&gcc GCC_USB3UNIPHY_PHY_MP1_BCR>;
2630 power-domains = <&gcc USB30_MP_GDSC>;
2644 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
2645 <&gcc GCC_USB3_SEC_CLKREF_CLK>,
2646 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>,
2647 <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
2652 resets = <&gcc GCC_USB3_DP_PHY_SEC_BCR>,
2653 <&gcc GCC_USB3_PHY_SEC_BCR>;
2715 clocks = <&gcc GCC_CFG_NOC_USB3_MP_AXI_CLK>,
2716 <&gcc GCC_USB30_MP_MASTER_CLK>,
2717 <&gcc GCC_AGGRE_USB3_MP_AXI_CLK>,
2718 <&gcc GCC_USB30_MP_SLEEP_CLK>,
2719 <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>,
2720 <&gcc GCC_USB3_SEC_CLKREF_CLK>;
2732 assigned-clocks = <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>,
2733 <&gcc GCC_USB30_MP_MASTER_CLK>;
2752 power-domains = <&gcc USB30_MP_GDSC>;
2754 resets = <&gcc GCC_USB30_MP_BCR>;
2791 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
2792 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
2793 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
2794 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
2795 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
2796 <&gcc GCC_USB3_SEC_CLKREF_CLK>;
2803 resets = <&gcc GCC_USB30_PRIM_BCR>;
2804 power-domains = <&gcc USB30_PRIM_GDSC>;
2810 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
2811 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
2857 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
2858 <&gcc GCC_USB30_SEC_MASTER_CLK>,
2859 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
2860 <&gcc GCC_USB30_SEC_SLEEP_CLK>,
2861 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
2862 <&gcc GCC_USB3_SEC_CLKREF_CLK>;
2869 resets = <&gcc GCC_USB30_SEC_BCR>;
2870 power-domains = <&gcc USB30_SEC_GDSC>;
2883 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
2884 <&gcc GCC_USB30_SEC_MASTER_CLK>;
2938 <&gcc GCC_DISP_HF_AXI_CLK>,
2939 <&gcc GCC_DISP_SF_AXI_CLK>,
2977 <&gcc GCC_DISP_HF_AXI_CLK>,
3076 <&gcc GCC_DISP_HF_AXI_CLK>;
3162 <&gcc GCC_DISP_HF_AXI_CLK>;
3861 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
3896 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;