Lines Matching +full:1 +full:c0e000
187 qcom,client-id = <1>;
301 clocks = <&cpufreq_hw 1>;
311 qcom,freq-domain = <&cpufreq_hw 1>;
325 clocks = <&cpufreq_hw 1>;
335 qcom,freq-domain = <&cpufreq_hw 1>;
349 clocks = <&cpufreq_hw 1>;
359 qcom,freq-domain = <&cpufreq_hw 1>;
442 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
452 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
462 BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
482 CLUSTER_SLEEP_CX_RET: cluster-sleep-1 {
744 #qcom,smem-state-cells = <1>;
768 #qcom,smem-state-cells = <1>;
788 qcom,remote-pid = <1>;
792 #qcom,smem-state-cells = <1>;
803 #qcom,smem-state-cells = <1>;
827 #qcom,smem-state-cells = <1>;
838 #qcom,smem-state-cells = <1>;
967 <&ufs_mem_phy 0>, <&ufs_mem_phy 1>, <&ufs_mem_phy 2>,
974 #clock-cells = <1>;
975 #reset-cells = <1>;
976 #power-domain-cells = <1>;
998 #address-cells = <1>;
999 #size-cells = <1>;
1001 gpu_speed_bin: gpu-speed-bin@1e9 {
1011 pinctrl-1 = <&sdc1_clk_sleep>, <&sdc1_cmd_sleep>, <&sdc1_data_sleep>, <&sdc1_rclk_sleep>;
1040 mmc-ddr-1_8v;
1041 mmc-hs200-1_8v;
1042 mmc-hs400-1_8v;
1108 #address-cells = <1>;
1118 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
1131 #address-cells = <1>;
1139 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
1168 #address-cells = <1>;
1177 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
1178 <&gpi_dma0 1 1 QCOM_GPI_I2C>;
1191 #address-cells = <1>;
1198 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1199 <&gpi_dma0 1 1 QCOM_GPI_SPI>;
1228 #address-cells = <1>;
1238 <&gpi_dma0 1 2 QCOM_GPI_I2C>;
1251 #address-cells = <1>;
1259 <&gpi_dma0 1 2 QCOM_GPI_SPI>;
1288 #address-cells = <1>;
1298 <&gpi_dma0 1 3 QCOM_GPI_I2C>;
1311 #address-cells = <1>;
1319 <&gpi_dma0 1 3 QCOM_GPI_SPI>;
1348 #address-cells = <1>;
1358 <&gpi_dma0 1 4 QCOM_GPI_I2C>;
1371 #address-cells = <1>;
1379 <&gpi_dma0 1 4 QCOM_GPI_SPI>;
1408 #address-cells = <1>;
1418 <&gpi_dma0 1 5 QCOM_GPI_I2C>;
1431 #address-cells = <1>;
1439 <&gpi_dma0 1 5 QCOM_GPI_SPI>;
1468 #address-cells = <1>;
1478 <&gpi_dma0 1 6 QCOM_GPI_I2C>;
1491 #address-cells = <1>;
1499 <&gpi_dma0 1 6 QCOM_GPI_SPI>;
1528 #address-cells = <1>;
1538 <&gpi_dma0 1 7 QCOM_GPI_I2C>;
1551 #address-cells = <1>;
1559 <&gpi_dma0 1 7 QCOM_GPI_SPI>;
1623 #address-cells = <1>;
1633 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1646 #address-cells = <1>;
1654 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1683 #address-cells = <1>;
1692 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1693 <&gpi_dma1 1 1 QCOM_GPI_I2C>;
1706 #address-cells = <1>;
1713 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1714 <&gpi_dma1 1 1 QCOM_GPI_SPI>;
1743 #address-cells = <1>;
1753 <&gpi_dma1 1 2 QCOM_GPI_I2C>;
1766 #address-cells = <1>;
1774 <&gpi_dma1 1 2 QCOM_GPI_SPI>;
1803 #address-cells = <1>;
1813 <&gpi_dma1 1 3 QCOM_GPI_I2C>;
1826 #address-cells = <1>;
1834 <&gpi_dma1 1 3 QCOM_GPI_SPI>;
1863 #address-cells = <1>;
1873 <&gpi_dma1 1 4 QCOM_GPI_I2C>;
1886 #address-cells = <1>;
1894 <&gpi_dma1 1 4 QCOM_GPI_SPI>;
1923 #address-cells = <1>;
1933 <&gpi_dma1 1 5 QCOM_GPI_I2C>;
1946 #address-cells = <1>;
1954 <&gpi_dma1 1 5 QCOM_GPI_SPI>;
1983 #address-cells = <1>;
1993 <&gpi_dma1 1 6 QCOM_GPI_I2C>;
2006 #address-cells = <1>;
2014 <&gpi_dma1 1 6 QCOM_GPI_SPI>;
2043 #address-cells = <1>;
2053 <&gpi_dma1 1 7 QCOM_GPI_I2C>;
2066 #address-cells = <1>;
2074 <&gpi_dma1 1 7 QCOM_GPI_SPI>;
2196 pcie1: pcie@1c08000 {
2206 linux,pci-domain = <1>;
2226 #interrupt-cells = <1>;
2228 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>,
2293 pcie1_phy: phy@1c0e000 {
2321 ufs_mem_hc: ufs@1d84000 {
2329 #reset-cells = <1>;
2375 ufs_mem_phy: phy@1d87000 {
2388 #clock-cells = <1>;
2394 ice: crypto@1d88000 {
2401 cryptobam: dma-controller@1dc4000 {
2405 #dma-cells = <1>;
2414 crypto: crypto@1dfa000 {
2425 ipa: ipa@1e40000 {
2440 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>;
2457 <&ipa_smp2p_out 1>;
2464 tcsr_mutex: hwlock@1f40000 {
2467 #hwlock-cells = <1>;
2470 tcsr_1: syscon@1f60000 {
2475 tcsr_2: syscon@1fc0000 {
2487 #clock-cells = <1>;
2508 #sound-dai-cells = <1>;
2537 #sound-dai-cells = <1>;
2561 #sound-dai-cells = <1>;
2591 #sound-dai-cells = <1>;
2606 #clock-cells = <1>;
2607 #power-domain-cells = <1>;
2608 #reset-cells = <1>;
2626 #sound-dai-cells = <1>;
2638 #clock-cells = <1>;
2639 #power-domain-cells = <1>;
2649 #clock-cells = <1>;
2650 #power-domain-cells = <1>;
2699 #sound-dai-cells = <1>;
2700 #address-cells = <1>;
2719 #dma-cells = <1>;
2722 qcom,ee = <1>;
2735 #address-cells = <1>;
2745 #clock-cells = <1>;
2746 #power-domain-cells = <1>;
2816 <&adreno_smmu 1 0x400>;
2855 opp-550000000-1 {
2948 #clock-cells = <1>;
2949 #reset-cells = <1>;
2950 #power-domain-cells = <1>;
3015 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
3045 qcom,remote-pid = <1>;
3083 #address-cells = <1>;
3111 #address-cells = <1>;
3139 #address-cells = <1>;
3149 port@1 {
3150 reg = <1>;
3216 #address-cells = <1>;
3453 #address-cells = <1>;
3463 port@1 {
3464 reg = <1>;
3542 pinctrl-1 = <&sdc2_clk_sleep>, <&sdc2_cmd_sleep>, <&sdc2_data_sleep>;
3632 #clock-cells = <1>;
3633 #phy-cells = <1>;
3636 #address-cells = <1>;
3646 port@1 {
3647 reg = <1>;
3728 #address-cells = <1>;
3748 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
3786 #address-cells = <1>;
3802 #address-cells = <1>;
3804 #sound-dai-cells = <1>;
3820 #address-cells = <1>;
3822 #sound-dai-cells = <1>;
3829 dai@1 {
3830 reg = <1>;
3856 #address-cells = <1>;
3886 <&wpss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
3938 opp-1 {
3977 opp-1 {
4029 #address-cells = <1>;
4054 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
4094 #address-cells = <1>;
4097 compute-cb@1 {
4099 reg = <1>;
4245 #address-cells = <1>;
4255 port@1 {
4256 reg = <1>;
4337 #clock-cells = <1>;
4338 #reset-cells = <1>;
4339 #power-domain-cells = <1>;
4359 pinctrl-1 = <&cci0_sleep &cci1_sleep>;
4362 #address-cells = <1>;
4370 #address-cells = <1>;
4374 cci0_i2c1: i2c-bus@1 {
4375 reg = <1>;
4377 #address-cells = <1>;
4399 pinctrl-1 = <&cci2_sleep &cci3_sleep>;
4402 #address-cells = <1>;
4410 #address-cells = <1>;
4414 cci1_i2c1: i2c-bus@1 {
4415 reg = <1>;
4417 #address-cells = <1>;
4429 #clock-cells = <1>;
4430 #reset-cells = <1>;
4431 #power-domain-cells = <1>;
4440 <&mdss_dsi_phy 1>,
4444 <&mdss_edp_phy 1>;
4453 #clock-cells = <1>;
4454 #reset-cells = <1>;
4455 #power-domain-cells = <1>;
4474 #interrupt-cells = <1>;
4520 #address-cells = <1>;
4530 port@1 {
4531 reg = <1>;
4598 assigned-clock-parents = <&mdss_dsi_phy 0>, <&mdss_dsi_phy 1>;
4605 #address-cells = <1>;
4611 #address-cells = <1>;
4621 port@1 {
4622 reg = <1>;
4657 #clock-cells = <1>;
4692 assigned-clock-parents = <&mdss_edp_phy 0>, <&mdss_edp_phy 1>;
4703 #address-cells = <1>;
4713 port@1 {
4714 reg = <1>;
4757 #clock-cells = <1>;
4800 #address-cells = <1>;
4810 port@1 {
4811 reg = <1>;
4845 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>,
4847 <64 434 2>, <66 438 3>, <69 86 1>,
4848 <70 520 54>, <124 609 31>, <155 63 1>,
4858 #reset-cells = <1>;
4870 #thermal-sensor-cells = <1>;
4881 #thermal-sensor-cells = <1>;
4887 #reset-cells = <1>;
4916 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
5782 #address-cells = <1>;
5783 #size-cells = <1>;
5797 #global-interrupts = <1>;
5974 #msi-cells = <1>;
5988 #address-cells = <1>;
5989 #size-cells = <1>;
6003 frame-number = <1>;
6050 reg-names = "drv-0", "drv-1", "drv-2";
6059 <CONTROL_TCS 1>;
6068 #power-domain-cells = <1>;
6116 #clock-cells = <1>;
6125 #interconnect-cells = <1>;
6138 "dcvsh-irq-1",
6143 #freq-domain-cells = <1>;
6144 #clock-cells = <1>;
6155 thermal-sensors = <&tsens0 1>;
6749 thermal-sensors = <&tsens1 1>;