Lines Matching full:mmcc
7 #include <dt-bindings/clock/qcom,mmcc-msm8998.h>
2746 mmcc: clock-controller@c8c0000 { label
2747 compatible = "qcom,mmcc-msm8998";
2784 clocks = <&mmcc MDSS_AHB_CLK>,
2785 <&mmcc MDSS_AXI_CLK>,
2786 <&mmcc MDSS_MDP_CLK>;
2791 power-domains = <&mmcc MDSS_GDSC>;
2814 clocks = <&mmcc MDSS_AHB_CLK>,
2815 <&mmcc MDSS_AXI_CLK>,
2816 <&mmcc MNOC_AHB_CLK>,
2817 <&mmcc MDSS_MDP_CLK>,
2818 <&mmcc MDSS_VSYNC_CLK>;
2825 assigned-clocks = <&mmcc MDSS_VSYNC_CLK>;
2885 clocks = <&mmcc MDSS_BYTE0_CLK>,
2886 <&mmcc MDSS_BYTE0_INTF_CLK>,
2887 <&mmcc MDSS_PCLK0_CLK>,
2888 <&mmcc MDSS_ESC0_CLK>,
2889 <&mmcc MDSS_AHB_CLK>,
2890 <&mmcc MDSS_AXI_CLK>;
2897 assigned-clocks = <&mmcc BYTE0_CLK_SRC>,
2898 <&mmcc PCLK0_CLK_SRC>;
2943 clocks = <&mmcc MDSS_AHB_CLK>,
2961 clocks = <&mmcc MDSS_BYTE1_CLK>,
2962 <&mmcc MDSS_BYTE1_INTF_CLK>,
2963 <&mmcc MDSS_PCLK1_CLK>,
2964 <&mmcc MDSS_ESC1_CLK>,
2965 <&mmcc MDSS_AHB_CLK>,
2966 <&mmcc MDSS_AXI_CLK>;
2973 assigned-clocks = <&mmcc BYTE1_CLK_SRC>,
2974 <&mmcc PCLK1_CLK_SRC>;
3019 clocks = <&mmcc MDSS_AHB_CLK>,
3035 power-domains = <&mmcc VIDEO_TOP_GDSC>;
3036 clocks = <&mmcc VIDEO_CORE_CLK>,
3037 <&mmcc VIDEO_AHB_CLK>,
3038 <&mmcc VIDEO_AXI_CLK>,
3039 <&mmcc VIDEO_MAXI_CLK>;
3066 clocks = <&mmcc VIDEO_SUBCORE0_CLK>;
3068 power-domains = <&mmcc VIDEO_SUBCORE0_GDSC>;
3073 clocks = <&mmcc VIDEO_SUBCORE1_CLK>;
3075 power-domains = <&mmcc VIDEO_SUBCORE1_GDSC>;
3084 clocks = <&mmcc MNOC_AHB_CLK>,
3085 <&mmcc BIMC_SMMU_AHB_CLK>,
3086 <&mmcc BIMC_SMMU_AXI_CLK>;
3114 power-domains = <&mmcc BIMC_SMMU_GDSC>;