dts/qcom/ipq9574.dtsi

10 #include <dt-bindings/clock/qcom,ipq9574-gcc.h>
13 #include <dt-bindings/reset/qcom,ipq9574-gcc.h>
232 			clocks = <&gcc GCC_PRNG_AHB_CLK>;
241 			clocks = <&gcc GCC_MDIO_AHB_CLK>;
270 			clocks = <&gcc GCC_CRYPTO_AHB_CLK>,
271 				 <&gcc GCC_CRYPTO_AXI_CLK>,
272 				 <&gcc GCC_CRYPTO_CLK>;
306 		gcc: clock-controller@1800000 {  label
307 			compatible = "qcom,ipq9574-gcc";
344 			clocks = <&gcc GCC_SDCC1_AHB_CLK>,
345 				 <&gcc GCC_SDCC1_APPS_CLK>,
347 				 <&gcc GCC_SDCC1_ICE_CORE_CLK>;
358 			clocks = <&gcc GCC_BLSP1_AHB_CLK>;
368 			clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
369 				 <&gcc GCC_BLSP1_AHB_CLK>;
378 			clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
379 				 <&gcc GCC_BLSP1_AHB_CLK>;
388 			clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,
389 				 <&gcc GCC_BLSP1_AHB_CLK>;
398 			clocks = <&gcc GCC_BLSP1_UART4_APPS_CLK>,
399 				 <&gcc GCC_BLSP1_AHB_CLK>;
408 			clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>,
409 				 <&gcc GCC_BLSP1_AHB_CLK>;
418 			clocks = <&gcc GCC_BLSP1_UART6_APPS_CLK>,
419 				 <&gcc GCC_BLSP1_AHB_CLK>;
430 			clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
431 				 <&gcc GCC_BLSP1_AHB_CLK>;
444 			clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
445 				 <&gcc GCC_BLSP1_AHB_CLK>;
447 			assigned-clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
460 			clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
461 				 <&gcc GCC_BLSP1_AHB_CLK>;
474 			clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
475 				 <&gcc GCC_BLSP1_AHB_CLK>;
477 			assigned-clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
490 			clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>,
491 				 <&gcc GCC_BLSP1_AHB_CLK>;
504 			clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
505 				 <&gcc GCC_BLSP1_AHB_CLK>;
507 			assigned-clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>;
521 			clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>,
522 				 <&gcc GCC_BLSP1_AHB_CLK>;
535 			clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>,
536 				 <&gcc GCC_BLSP1_AHB_CLK>;
538 			assigned-clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>;
551 			clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>,
552 				 <&gcc GCC_BLSP1_AHB_CLK>;
564 			clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
569 			resets = <&gcc GCC_QUSB2_0_PHY_BCR>;
578 			clocks = <&gcc GCC_USB0_AUX_CLK>,
580 				 <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
581 				 <&gcc GCC_USB0_PIPE_CLK>;
587 			resets = <&gcc GCC_USB0_PHY_BCR>,
588 				 <&gcc GCC_USB3PHY_0_PHY_BCR>;
605 			clocks = <&gcc GCC_SNOC_USB_CLK>,
606 				 <&gcc GCC_USB0_MASTER_CLK>,
607 				 <&gcc GCC_ANOC_USB_AXI_CLK>,
608 				 <&gcc GCC_USB0_SLEEP_CLK>,
609 				 <&gcc GCC_USB0_MOCK_UTMI_CLK>;
617 			assigned-clocks = <&gcc GCC_USB0_MASTER_CLK>,
618 					  <&gcc GCC_USB0_MOCK_UTMI_CLK>;
625 			resets = <&gcc GCC_USB_BCR>;
631 				clocks = <&gcc GCC_USB0_MOCK_UTMI_CLK>;
689 			clocks = <&a73pll>, <&xo_board_clk>, <&gcc GPLL0>;