Lines Matching +full:gcc +full:- +full:ipq6018
1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/qcom,gcc-ipq8074.h>
10 #address-cells = <2>;
11 #size-cells = <2>;
15 interrupt-parent = <&intc>;
19 compatible = "fixed-clock";
20 clock-frequency = <32768>;
21 #clock-cells = <0>;
25 compatible = "fixed-clock";
26 clock-frequency = <19200000>;
27 #clock-cells = <0>;
32 #address-cells = <1>;
33 #size-cells = <0>;
37 compatible = "arm,cortex-a53";
39 next-level-cache = <&L2_0>;
40 enable-method = "psci";
45 compatible = "arm,cortex-a53";
46 enable-method = "psci";
48 next-level-cache = <&L2_0>;
53 compatible = "arm,cortex-a53";
54 enable-method = "psci";
56 next-level-cache = <&L2_0>;
61 compatible = "arm,cortex-a53";
62 enable-method = "psci";
64 next-level-cache = <&L2_0>;
67 L2_0: l2-cache {
69 cache-level = <2>;
70 cache-unified;
75 compatible = "arm,cortex-a53-pmu";
80 compatible = "arm,psci-1.0";
84 reserved-memory {
85 #address-cells = <2>;
86 #size-cells = <2>;
91 no-map;
96 no-map;
102 no-map;
109 no-map;
115 compatible = "qcom,scm-ipq8074", "qcom,scm";
116 qcom,dload-mode = <&tcsr 0x6100>;
121 #address-cells = <1>;
122 #size-cells = <1>;
124 compatible = "simple-bus";
127 compatible = "qcom,ipq8074-qmp-usb3-phy";
130 clocks = <&gcc GCC_USB1_AUX_CLK>,
132 <&gcc GCC_USB1_PHY_CFG_AHB_CLK>,
133 <&gcc GCC_USB1_PIPE_CLK>;
134 clock-names = "aux",
138 clock-output-names = "usb3phy_1_cc_pipe_clk";
139 #clock-cells = <0>;
140 #phy-cells = <0>;
142 resets = <&gcc GCC_USB1_PHY_BCR>,
143 <&gcc GCC_USB3PHY_1_PHY_BCR>;
144 reset-names = "phy",
151 compatible = "qcom,ipq8074-qusb2-phy";
153 #phy-cells = <0>;
155 clocks = <&gcc GCC_USB1_PHY_CFG_AHB_CLK>,
157 clock-names = "cfg_ahb", "ref";
159 resets = <&gcc GCC_QUSB2_1_PHY_BCR>;
164 compatible = "qcom,ipq8074-qmp-usb3-phy";
167 clocks = <&gcc GCC_USB0_AUX_CLK>,
169 <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
170 <&gcc GCC_USB0_PIPE_CLK>;
171 clock-names = "aux",
175 clock-output-names = "usb3phy_0_cc_pipe_clk";
176 #clock-cells = <0>;
177 #phy-cells = <0>;
179 resets = <&gcc GCC_USB0_PHY_BCR>,
180 <&gcc GCC_USB3PHY_0_PHY_BCR>;
181 reset-names = "phy",
188 compatible = "qcom,ipq8074-qusb2-phy";
190 #phy-cells = <0>;
192 clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
194 clock-names = "cfg_ahb", "ref";
196 resets = <&gcc GCC_QUSB2_0_PHY_BCR>;
201 compatible = "qcom,ipq8074-qmp-gen3-pcie-phy";
204 clocks = <&gcc GCC_PCIE0_AUX_CLK>,
205 <&gcc GCC_PCIE0_AHB_CLK>,
206 <&gcc GCC_PCIE0_PIPE_CLK>;
207 clock-names = "aux",
211 clock-output-names = "pcie20_phy0_pipe_clk";
212 #clock-cells = <0>;
214 #phy-cells = <0>;
216 resets = <&gcc GCC_PCIE0_PHY_BCR>,
217 <&gcc GCC_PCIE0PHY_PHY_BCR>;
218 reset-names = "phy",
224 compatible = "qcom,ipq8074-qmp-pcie-phy";
227 clocks = <&gcc GCC_PCIE1_AUX_CLK>,
228 <&gcc GCC_PCIE1_AHB_CLK>,
229 <&gcc GCC_PCIE1_PIPE_CLK>;
230 clock-names = "aux",
234 clock-output-names = "pcie20_phy1_pipe_clk";
235 #clock-cells = <0>;
237 #phy-cells = <0>;
239 resets = <&gcc GCC_PCIE1_PHY_BCR>,
240 <&gcc GCC_PCIE1PHY_PHY_BCR>;
241 reset-names = "phy",
247 compatible = "qcom,ipq8074-mdio", "qcom,ipq4019-mdio";
249 #address-cells = <1>;
250 #size-cells = <0>;
252 clocks = <&gcc GCC_MDIO_AHB_CLK>;
253 clock-names = "gcc_mdio_ahb_clk";
255 clock-frequency = <6250000>;
261 compatible = "qcom,ipq8074-qfprom", "qcom,qfprom";
263 #address-cells = <1>;
264 #size-cells = <1>;
268 compatible = "qcom,prng-ee";
270 clocks = <&gcc GCC_PRNG_AHB_CLK>;
271 clock-names = "core";
275 tsens: thermal-sensor@4a9000 {
276 compatible = "qcom,ipq8074-tsens";
280 interrupt-names = "combined";
282 #thermal-sensor-cells = <1>;
285 cryptobam: dma-controller@704000 {
286 compatible = "qcom,bam-v1.7.0";
289 clocks = <&gcc GCC_CRYPTO_AHB_CLK>;
290 clock-names = "bam_clk";
291 #dma-cells = <1>;
293 qcom,controlled-remotely;
298 compatible = "qcom,crypto-v5.1";
300 clocks = <&gcc GCC_CRYPTO_AHB_CLK>,
301 <&gcc GCC_CRYPTO_AXI_CLK>,
302 <&gcc GCC_CRYPTO_CLK>;
303 clock-names = "iface", "bus", "core";
305 dma-names = "rx", "tx";
310 compatible = "qcom,ipq8074-pinctrl";
313 gpio-controller;
314 gpio-ranges = <&tlmm 0 0 70>;
315 #gpio-cells = <2>;
316 interrupt-controller;
317 #interrupt-cells = <2>;
319 serial_4_pins: serial4-state {
322 drive-strength = <8>;
323 bias-disable;
326 serial_5_pins: serial5-state {
329 drive-strength = <8>;
330 bias-disable;
333 i2c_0_pins: i2c-0-state {
336 drive-strength = <8>;
337 bias-disable;
340 spi_0_pins: spi-0-state {
343 drive-strength = <8>;
344 bias-disable;
347 hsuart_pins: hsuart-state {
350 drive-strength = <8>;
351 bias-disable;
354 qpic_pins: qpic-state {
361 drive-strength = <8>;
362 bias-disable;
366 gcc: clock-controller@1800000 { label
367 compatible = "qcom,gcc-ipq8074";
373 clock-names = "xo",
377 #clock-cells = <1>;
378 #power-domain-cells = <1>;
379 #reset-cells = <1>;
383 compatible = "qcom,tcsr-mutex";
385 #hwlock-cells = <1>;
389 compatible = "qcom,tcsr-ipq8074", "syscon";
394 compatible = "qcom,spmi-pmic-arb";
400 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
402 interrupt-names = "periph_irq";
405 #address-cells = <2>;
406 #size-cells = <0>;
407 interrupt-controller;
408 #interrupt-cells = <4>;
412 compatible = "qcom,ipq8074-sdhci", "qcom,sdhci-msm-v4";
414 reg-names = "hc", "core";
418 interrupt-names = "hc_irq", "pwr_irq";
420 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
421 <&gcc GCC_SDCC1_APPS_CLK>,
423 clock-names = "iface", "core", "xo";
424 resets = <&gcc GCC_SDCC1_BCR>;
425 max-frequency = <384000000>;
426 mmc-ddr-1_8v;
427 mmc-hs200-1_8v;
428 mmc-hs400-1_8v;
429 bus-width = <8>;
434 blsp_dma: dma-controller@7884000 {
435 compatible = "qcom,bam-v1.7.0";
438 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
439 clock-names = "bam_clk";
440 #dma-cells = <1>;
445 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
448 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
449 <&gcc GCC_BLSP1_AHB_CLK>;
450 clock-names = "core", "iface";
455 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
458 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,
459 <&gcc GCC_BLSP1_AHB_CLK>;
460 clock-names = "core", "iface";
463 dma-names = "tx", "rx";
464 pinctrl-0 = <&hsuart_pins>;
465 pinctrl-names = "default";
470 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
473 clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>,
474 <&gcc GCC_BLSP1_AHB_CLK>;
475 clock-names = "core", "iface";
476 pinctrl-0 = <&serial_4_pins>;
477 pinctrl-names = "default";
482 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
485 clocks = <&gcc GCC_BLSP1_UART6_APPS_CLK>,
486 <&gcc GCC_BLSP1_AHB_CLK>;
487 clock-names = "core", "iface";
488 pinctrl-0 = <&serial_5_pins>;
489 pinctrl-names = "default";
494 compatible = "qcom,spi-qup-v2.2.1";
495 #address-cells = <1>;
496 #size-cells = <0>;
499 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
500 <&gcc GCC_BLSP1_AHB_CLK>;
501 clock-names = "core", "iface";
503 dma-names = "tx", "rx";
504 pinctrl-0 = <&spi_0_pins>;
505 pinctrl-names = "default";
510 compatible = "qcom,i2c-qup-v2.2.1";
511 #address-cells = <1>;
512 #size-cells = <0>;
515 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
516 <&gcc GCC_BLSP1_AHB_CLK>;
517 clock-names = "core", "iface";
518 clock-frequency = <400000>;
520 dma-names = "tx", "rx";
521 pinctrl-0 = <&i2c_0_pins>;
522 pinctrl-names = "default";
527 compatible = "qcom,i2c-qup-v2.2.1";
528 #address-cells = <1>;
529 #size-cells = <0>;
532 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
533 <&gcc GCC_BLSP1_AHB_CLK>;
534 clock-names = "core", "iface";
535 clock-frequency = <100000>;
537 dma-names = "tx", "rx";
542 compatible = "qcom,spi-qup-v2.2.1";
543 #address-cells = <1>;
544 #size-cells = <0>;
547 clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>,
548 <&gcc GCC_BLSP1_AHB_CLK>;
549 clock-names = "core", "iface";
551 dma-names = "tx", "rx";
556 compatible = "qcom,i2c-qup-v2.2.1";
557 #address-cells = <1>;
558 #size-cells = <0>;
561 clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>,
562 <&gcc GCC_BLSP1_AHB_CLK>;
563 clock-names = "core", "iface";
564 clock-frequency = <400000>;
566 dma-names = "tx", "rx";
571 compatible = "qcom,spi-qup-v2.2.1";
572 #address-cells = <1>;
573 #size-cells = <0>;
576 clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>,
577 <&gcc GCC_BLSP1_AHB_CLK>;
578 clock-names = "core", "iface";
580 dma-names = "tx", "rx";
585 compatible = "qcom,i2c-qup-v2.2.1";
586 #address-cells = <1>;
587 #size-cells = <0>;
590 clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>,
591 <&gcc GCC_BLSP1_AHB_CLK>;
592 clock-names = "core", "iface";
593 clock-frequency = <100000>;
595 dma-names = "tx", "rx";
599 qpic_bam: dma-controller@7984000 {
600 compatible = "qcom,bam-v1.7.0";
603 clocks = <&gcc GCC_QPIC_AHB_CLK>;
604 clock-names = "bam_clk";
605 #dma-cells = <1>;
610 qpic_nand: nand-controller@79b0000 {
611 compatible = "qcom,ipq8074-nand";
613 #address-cells = <1>;
614 #size-cells = <0>;
615 clocks = <&gcc GCC_QPIC_CLK>,
616 <&gcc GCC_QPIC_AHB_CLK>;
617 clock-names = "core", "aon";
622 dma-names = "tx", "rx", "cmd";
623 pinctrl-0 = <&qpic_pins>;
624 pinctrl-names = "default";
629 compatible = "qcom,ipq8074-dwc3", "qcom,dwc3";
631 #address-cells = <1>;
632 #size-cells = <1>;
635 clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
636 <&gcc GCC_USB0_MASTER_CLK>,
637 <&gcc GCC_USB0_SLEEP_CLK>,
638 <&gcc GCC_USB0_MOCK_UTMI_CLK>;
639 clock-names = "cfg_noc",
644 assigned-clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
645 <&gcc GCC_USB0_MASTER_CLK>,
646 <&gcc GCC_USB0_MOCK_UTMI_CLK>;
647 assigned-clock-rates = <133330000>,
654 interrupt-names = "pwr_event",
658 power-domains = <&gcc USB0_GDSC>;
660 resets = <&gcc GCC_USB0_BCR>;
668 phy-names = "usb2-phy", "usb3-phy";
669 snps,parkmode-disable-ss-quirk;
670 snps,is-utmi-l1-suspend;
671 snps,hird-threshold = /bits/ 8 <0x0>;
679 compatible = "qcom,ipq8074-dwc3", "qcom,dwc3";
681 #address-cells = <1>;
682 #size-cells = <1>;
685 clocks = <&gcc GCC_SYS_NOC_USB1_AXI_CLK>,
686 <&gcc GCC_USB1_MASTER_CLK>,
687 <&gcc GCC_USB1_SLEEP_CLK>,
688 <&gcc GCC_USB1_MOCK_UTMI_CLK>;
689 clock-names = "cfg_noc",
694 assigned-clocks = <&gcc GCC_SYS_NOC_USB1_AXI_CLK>,
695 <&gcc GCC_USB1_MASTER_CLK>,
696 <&gcc GCC_USB1_MOCK_UTMI_CLK>;
697 assigned-clock-rates = <133330000>,
704 interrupt-names = "pwr_event",
708 power-domains = <&gcc USB1_GDSC>;
710 resets = <&gcc GCC_USB1_BCR>;
718 phy-names = "usb2-phy", "usb3-phy";
719 snps,parkmode-disable-ss-quirk;
720 snps,is-utmi-l1-suspend;
721 snps,hird-threshold = /bits/ 8 <0x0>;
728 intc: interrupt-controller@b000000 {
729 compatible = "qcom,msm-qgic2";
730 #address-cells = <1>;
731 #size-cells = <1>;
732 interrupt-controller;
733 #interrupt-cells = <3>;
738 compatible = "arm,gic-v2m-frame";
739 msi-controller;
745 compatible = "qcom,kpss-wdt";
749 timeout-sec = <30>;
753 compatible = "qcom,ipq8074-apcs-apps-global",
754 "qcom,ipq6018-apcs-apps-global";
756 clocks = <&a53pll>, <&xo>, <&gcc GPLL0>;
757 clock-names = "pll", "xo", "gpll0";
759 #clock-cells = <1>;
760 #mbox-cells = <1>;
764 compatible = "qcom,ipq8074-a53pll";
766 #clock-cells = <0>;
768 clock-names = "xo";
772 #address-cells = <1>;
773 #size-cells = <1>;
775 compatible = "arm,armv7-timer-mem";
779 frame-number = <0>;
787 frame-number = <1>;
794 frame-number = <2>;
801 frame-number = <3>;
808 frame-number = <4>;
815 frame-number = <5>;
822 frame-number = <6>;
830 compatible = "qcom,pcie-ipq8074";
835 reg-names = "dbi", "elbi", "parf", "config";
837 linux,pci-domain = <1>;
838 bus-range = <0x00 0xff>;
839 num-lanes = <1>;
840 max-link-speed = <2>;
841 #address-cells = <3>;
842 #size-cells = <2>;
845 phy-names = "pciephy";
851 interrupt-names = "msi";
852 #interrupt-cells = <1>;
853 interrupt-map-mask = <0 0 0 0x7>;
854 interrupt-map = <0 0 0 1 &intc 0 0 142
863 clocks = <&gcc GCC_SYS_NOC_PCIE1_AXI_CLK>,
864 <&gcc GCC_PCIE1_AXI_M_CLK>,
865 <&gcc GCC_PCIE1_AXI_S_CLK>,
866 <&gcc GCC_PCIE1_AHB_CLK>,
867 <&gcc GCC_PCIE1_AUX_CLK>;
868 clock-names = "iface",
873 resets = <&gcc GCC_PCIE1_PIPE_ARES>,
874 <&gcc GCC_PCIE1_SLEEP_ARES>,
875 <&gcc GCC_PCIE1_CORE_STICKY_ARES>,
876 <&gcc GCC_PCIE1_AXI_MASTER_ARES>,
877 <&gcc GCC_PCIE1_AXI_SLAVE_ARES>,
878 <&gcc GCC_PCIE1_AHB_ARES>,
879 <&gcc GCC_PCIE1_AXI_MASTER_STICKY_ARES>;
880 reset-names = "pipe",
892 bus-range = <0x01 0xff>;
894 #address-cells = <3>;
895 #size-cells = <2>;
901 compatible = "qcom,pcie-ipq8074-gen3";
907 reg-names = "dbi", "elbi", "atu", "parf", "config";
909 linux,pci-domain = <0>;
910 bus-range = <0x00 0xff>;
911 num-lanes = <1>;
912 max-link-speed = <3>;
913 #address-cells = <3>;
914 #size-cells = <2>;
917 phy-names = "pciephy";
923 interrupt-names = "msi";
924 #interrupt-cells = <1>;
925 interrupt-map-mask = <0 0 0 0x7>;
926 interrupt-map = <0 0 0 1 &intc 0 0 75
935 clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>,
936 <&gcc GCC_PCIE0_AXI_M_CLK>,
937 <&gcc GCC_PCIE0_AXI_S_CLK>,
938 <&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>,
939 <&gcc GCC_PCIE0_RCHNG_CLK>;
940 clock-names = "iface",
946 resets = <&gcc GCC_PCIE0_PIPE_ARES>,
947 <&gcc GCC_PCIE0_SLEEP_ARES>,
948 <&gcc GCC_PCIE0_CORE_STICKY_ARES>,
949 <&gcc GCC_PCIE0_AXI_MASTER_ARES>,
950 <&gcc GCC_PCIE0_AXI_SLAVE_ARES>,
951 <&gcc GCC_PCIE0_AHB_ARES>,
952 <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>,
953 <&gcc GCC_PCIE0_AXI_SLAVE_STICKY_ARES>;
954 reset-names = "pipe",
967 bus-range = <0x01 0xff>;
969 #address-cells = <3>;
970 #size-cells = <2>;
977 compatible = "arm,armv8-timer";
984 thermal-zones {
985 nss-top-thermal {
986 polling-delay-passive = <250>;
988 thermal-sensors = <&tsens 4>;
991 nss-top-crit {
999 nss0-thermal {
1000 polling-delay-passive = <250>;
1002 thermal-sensors = <&tsens 5>;
1005 nss-0-crit {
1013 nss1-thermal {
1014 polling-delay-passive = <250>;
1016 thermal-sensors = <&tsens 6>;
1019 nss-1-crit {
1027 wcss-phya0-thermal {
1028 polling-delay-passive = <250>;
1030 thermal-sensors = <&tsens 7>;
1033 wcss-phya0-crit {
1041 wcss-phya1-thermal {
1042 polling-delay-passive = <250>;
1044 thermal-sensors = <&tsens 8>;
1047 wcss-phya1-crit {
1055 cpu0_thermal: cpu0-thermal {
1056 polling-delay-passive = <250>;
1058 thermal-sensors = <&tsens 9>;
1061 cpu0-crit {
1069 cpu1_thermal: cpu1-thermal {
1070 polling-delay-passive = <250>;
1072 thermal-sensors = <&tsens 10>;
1075 cpu1-crit {
1083 cpu2_thermal: cpu2-thermal {
1084 polling-delay-passive = <250>;
1086 thermal-sensors = <&tsens 11>;
1089 cpu2-crit {
1097 cpu3_thermal: cpu3-thermal {
1098 polling-delay-passive = <250>;
1100 thermal-sensors = <&tsens 12>;
1103 cpu3-crit {
1111 cluster_thermal: cluster-thermal {
1112 polling-delay-passive = <250>;
1114 thermal-sensors = <&tsens 13>;
1117 cluster-crit {
1125 wcss-phyb0-thermal {
1126 polling-delay-passive = <250>;
1128 thermal-sensors = <&tsens 14>;
1131 wcss-phyb0-crit {
1139 wcss-phyb1-thermal {
1140 polling-delay-passive = <250>;
1142 thermal-sensors = <&tsens 15>;
1145 wcss-phyb1-crit {