Lines Matching full:gcc
7 #include <dt-bindings/clock/qcom,gcc-ipq8074.h>
130 clocks = <&gcc GCC_USB1_AUX_CLK>,
132 <&gcc GCC_USB1_PHY_CFG_AHB_CLK>,
133 <&gcc GCC_USB1_PIPE_CLK>;
142 resets = <&gcc GCC_USB1_PHY_BCR>,
143 <&gcc GCC_USB3PHY_1_PHY_BCR>;
155 clocks = <&gcc GCC_USB1_PHY_CFG_AHB_CLK>,
159 resets = <&gcc GCC_QUSB2_1_PHY_BCR>;
167 clocks = <&gcc GCC_USB0_AUX_CLK>,
169 <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
170 <&gcc GCC_USB0_PIPE_CLK>;
179 resets = <&gcc GCC_USB0_PHY_BCR>,
180 <&gcc GCC_USB3PHY_0_PHY_BCR>;
192 clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
196 resets = <&gcc GCC_QUSB2_0_PHY_BCR>;
204 clocks = <&gcc GCC_PCIE0_AUX_CLK>,
205 <&gcc GCC_PCIE0_AHB_CLK>,
206 <&gcc GCC_PCIE0_PIPE_CLK>;
216 resets = <&gcc GCC_PCIE0_PHY_BCR>,
217 <&gcc GCC_PCIE0PHY_PHY_BCR>;
227 clocks = <&gcc GCC_PCIE1_AUX_CLK>,
228 <&gcc GCC_PCIE1_AHB_CLK>,
229 <&gcc GCC_PCIE1_PIPE_CLK>;
239 resets = <&gcc GCC_PCIE1_PHY_BCR>,
240 <&gcc GCC_PCIE1PHY_PHY_BCR>;
252 clocks = <&gcc GCC_MDIO_AHB_CLK>;
270 clocks = <&gcc GCC_PRNG_AHB_CLK>;
289 clocks = <&gcc GCC_CRYPTO_AHB_CLK>;
300 clocks = <&gcc GCC_CRYPTO_AHB_CLK>,
301 <&gcc GCC_CRYPTO_AXI_CLK>,
302 <&gcc GCC_CRYPTO_CLK>;
366 gcc: clock-controller@1800000 { label
367 compatible = "qcom,gcc-ipq8074";
420 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
421 <&gcc GCC_SDCC1_APPS_CLK>,
424 resets = <&gcc GCC_SDCC1_BCR>;
438 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
448 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
449 <&gcc GCC_BLSP1_AHB_CLK>;
458 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,
459 <&gcc GCC_BLSP1_AHB_CLK>;
473 clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>,
474 <&gcc GCC_BLSP1_AHB_CLK>;
485 clocks = <&gcc GCC_BLSP1_UART6_APPS_CLK>,
486 <&gcc GCC_BLSP1_AHB_CLK>;
499 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
500 <&gcc GCC_BLSP1_AHB_CLK>;
515 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
516 <&gcc GCC_BLSP1_AHB_CLK>;
532 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
533 <&gcc GCC_BLSP1_AHB_CLK>;
547 clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>,
548 <&gcc GCC_BLSP1_AHB_CLK>;
561 clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>,
562 <&gcc GCC_BLSP1_AHB_CLK>;
576 clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>,
577 <&gcc GCC_BLSP1_AHB_CLK>;
590 clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>,
591 <&gcc GCC_BLSP1_AHB_CLK>;
603 clocks = <&gcc GCC_QPIC_AHB_CLK>;
615 clocks = <&gcc GCC_QPIC_CLK>,
616 <&gcc GCC_QPIC_AHB_CLK>;
635 clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
636 <&gcc GCC_USB0_MASTER_CLK>,
637 <&gcc GCC_USB0_SLEEP_CLK>,
638 <&gcc GCC_USB0_MOCK_UTMI_CLK>;
644 assigned-clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
645 <&gcc GCC_USB0_MASTER_CLK>,
646 <&gcc GCC_USB0_MOCK_UTMI_CLK>;
658 power-domains = <&gcc USB0_GDSC>;
660 resets = <&gcc GCC_USB0_BCR>;
685 clocks = <&gcc GCC_SYS_NOC_USB1_AXI_CLK>,
686 <&gcc GCC_USB1_MASTER_CLK>,
687 <&gcc GCC_USB1_SLEEP_CLK>,
688 <&gcc GCC_USB1_MOCK_UTMI_CLK>;
694 assigned-clocks = <&gcc GCC_SYS_NOC_USB1_AXI_CLK>,
695 <&gcc GCC_USB1_MASTER_CLK>,
696 <&gcc GCC_USB1_MOCK_UTMI_CLK>;
708 power-domains = <&gcc USB1_GDSC>;
710 resets = <&gcc GCC_USB1_BCR>;
756 clocks = <&a53pll>, <&xo>, <&gcc GPLL0>;
863 clocks = <&gcc GCC_SYS_NOC_PCIE1_AXI_CLK>,
864 <&gcc GCC_PCIE1_AXI_M_CLK>,
865 <&gcc GCC_PCIE1_AXI_S_CLK>,
866 <&gcc GCC_PCIE1_AHB_CLK>,
867 <&gcc GCC_PCIE1_AUX_CLK>;
873 resets = <&gcc GCC_PCIE1_PIPE_ARES>,
874 <&gcc GCC_PCIE1_SLEEP_ARES>,
875 <&gcc GCC_PCIE1_CORE_STICKY_ARES>,
876 <&gcc GCC_PCIE1_AXI_MASTER_ARES>,
877 <&gcc GCC_PCIE1_AXI_SLAVE_ARES>,
878 <&gcc GCC_PCIE1_AHB_ARES>,
879 <&gcc GCC_PCIE1_AXI_MASTER_STICKY_ARES>;
935 clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>,
936 <&gcc GCC_PCIE0_AXI_M_CLK>,
937 <&gcc GCC_PCIE0_AXI_S_CLK>,
938 <&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>,
939 <&gcc GCC_PCIE0_RCHNG_CLK>;
946 resets = <&gcc GCC_PCIE0_PIPE_ARES>,
947 <&gcc GCC_PCIE0_SLEEP_ARES>,
948 <&gcc GCC_PCIE0_CORE_STICKY_ARES>,
949 <&gcc GCC_PCIE0_AXI_MASTER_ARES>,
950 <&gcc GCC_PCIE0_AXI_SLAVE_ARES>,
951 <&gcc GCC_PCIE0_AHB_ARES>,
952 <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>,
953 <&gcc GCC_PCIE0_AXI_SLAVE_STICKY_ARES>;