dts/qcom/ipq6018.dtsi

9 #include <dt-bindings/clock/qcom,gcc-ipq6018.h>
10 #include <dt-bindings/reset/qcom,gcc-ipq6018.h>
241 			clocks = <&gcc GCC_USB1_PHY_CFG_AHB_CLK>,
245 			resets = <&gcc GCC_QUSB2_1_PHY_BCR>;
253 			clocks = <&gcc GCC_USB0_AUX_CLK>,
255 				 <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
256 				 <&gcc GCC_USB0_PIPE_CLK>;
265 			resets = <&gcc GCC_USB0_PHY_BCR>,
266 				 <&gcc GCC_USB3PHY_0_PHY_BCR>;
278 			clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
282 			resets = <&gcc GCC_QUSB2_0_PHY_BCR>;
291 			clocks = <&gcc GCC_PCIE0_AUX_CLK>,
292 				<&gcc GCC_PCIE0_AHB_CLK>,
293 				<&gcc GCC_PCIE0_PIPE_CLK>;
303 			resets = <&gcc GCC_PCIE0_PHY_BCR>,
304 				<&gcc GCC_PCIE0PHY_PHY_BCR>;
314 			clocks = <&gcc GCC_MDIO_AHB_CLK>;
334 			clocks = <&gcc GCC_PRNG_AHB_CLK>;
352 			clocks = <&gcc GCC_CRYPTO_AHB_CLK>;
362 			clocks = <&gcc GCC_CRYPTO_AHB_CLK>,
363 				 <&gcc GCC_CRYPTO_AXI_CLK>,
364 				 <&gcc GCC_CRYPTO_CLK>;
399 		gcc: clock-controller@1800000 {  label
400 			compatible = "qcom,gcc-ipq6018";
425 			clocks = <&gcc GCC_USB1_MASTER_CLK>,
426 				 <&gcc GCC_USB1_SLEEP_CLK>,
427 				 <&gcc GCC_USB1_MOCK_UTMI_CLK>;
432 			assigned-clocks = <&gcc GCC_USB1_MASTER_CLK>,
433 					  <&gcc GCC_USB1_MOCK_UTMI_CLK>;
442 			resets = <&gcc GCC_USB1_BCR>;
470 			clocks = <&gcc GCC_SDCC1_AHB_CLK>,
471 				 <&gcc GCC_SDCC1_APPS_CLK>,
474 			resets = <&gcc GCC_SDCC1_BCR>;
483 			clocks = <&gcc GCC_BLSP1_AHB_CLK>;
493 			clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
494 				 <&gcc GCC_BLSP1_AHB_CLK>;
503 			clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
504 				 <&gcc GCC_BLSP1_AHB_CLK>;
513 			clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,
514 				 <&gcc GCC_BLSP1_AHB_CLK>;
523 			clocks = <&gcc GCC_BLSP1_UART4_APPS_CLK>,
524 				 <&gcc GCC_BLSP1_AHB_CLK>;
533 			clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>,
534 				 <&gcc GCC_BLSP1_AHB_CLK>;
543 			clocks = <&gcc GCC_BLSP1_UART6_APPS_CLK>,
544 				 <&gcc GCC_BLSP1_AHB_CLK>;
555 			clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
556 				 <&gcc GCC_BLSP1_AHB_CLK>;
569 			clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
570 				 <&gcc GCC_BLSP1_AHB_CLK>;
583 			clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>,
584 				 <&gcc GCC_BLSP1_AHB_CLK>;
597 			clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
598 				 <&gcc GCC_BLSP1_AHB_CLK>;
612 			clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
613 				 <&gcc GCC_BLSP1_AHB_CLK>;
627 			clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>,
628 			       <&gcc GCC_BLSP1_AHB_CLK>;
640 			clocks = <&gcc GCC_QPIC_AHB_CLK>;
652 			clocks = <&gcc GCC_QPIC_CLK>,
653 				 <&gcc GCC_QPIC_AHB_CLK>;
672 			clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
673 				<&gcc GCC_USB0_MASTER_CLK>,
674 				<&gcc GCC_USB0_SLEEP_CLK>,
675 				<&gcc GCC_USB0_MOCK_UTMI_CLK>;
681 			assigned-clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
682 					  <&gcc GCC_USB0_MASTER_CLK>,
683 					  <&gcc GCC_USB0_MOCK_UTMI_CLK>;
695 			resets = <&gcc GCC_USB0_BCR>;
748 			clocks = <&a53pll>, <&xo>, <&gcc GPLL0>;
836 			resets = <&gcc GCC_WCSSAON_RESET>,
837 				 <&gcc GCC_WCSS_BCR>,
838 				 <&gcc GCC_WCSS_Q6_BCR>;
844 			clocks = <&gcc GCC_PRNG_AHB_CLK>;
901 			clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>,
902 				 <&gcc GCC_PCIE0_AXI_M_CLK>,
903 				 <&gcc GCC_PCIE0_AXI_S_CLK>,
904 				 <&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>,
905 				 <&gcc PCIE0_RCHNG_CLK>;
912 			resets = <&gcc GCC_PCIE0_PIPE_ARES>,
913 				 <&gcc GCC_PCIE0_SLEEP_ARES>,
914 				 <&gcc GCC_PCIE0_CORE_STICKY_ARES>,
915 				 <&gcc GCC_PCIE0_AXI_MASTER_ARES>,
916 				 <&gcc GCC_PCIE0_AXI_SLAVE_ARES>,
917 				 <&gcc GCC_PCIE0_AHB_ARES>,
918 				 <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>,
919 				 <&gcc GCC_PCIE0_AXI_SLAVE_STICKY_ARES>;