Lines Matching +full:tcsr +full:- +full:reg
1 // SPDX-License-Identifier: BSD-3-Clause
5 * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
8 #include <dt-bindings/clock/qcom,apss-ipq.h>
9 #include <dt-bindings/clock/qcom,ipq5332-gcc.h>
10 #include <dt-bindings/interconnect/qcom,ipq5332.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 interrupt-parent = <&intc>;
15 #address-cells = <2>;
16 #size-cells = <2>;
19 sleep_clk: sleep-clk {
20 compatible = "fixed-clock";
21 #clock-cells = <0>;
24 xo_board: xo-board-clk {
25 compatible = "fixed-clock";
26 #clock-cells = <0>;
31 #address-cells = <1>;
32 #size-cells = <0>;
36 compatible = "arm,cortex-a53";
37 reg = <0x0>;
38 enable-method = "psci";
39 next-level-cache = <&L2_0>;
41 operating-points-v2 = <&cpu_opp_table>;
46 compatible = "arm,cortex-a53";
47 reg = <0x1>;
48 enable-method = "psci";
49 next-level-cache = <&L2_0>;
51 operating-points-v2 = <&cpu_opp_table>;
56 compatible = "arm,cortex-a53";
57 reg = <0x2>;
58 enable-method = "psci";
59 next-level-cache = <&L2_0>;
61 operating-points-v2 = <&cpu_opp_table>;
66 compatible = "arm,cortex-a53";
67 reg = <0x3>;
68 enable-method = "psci";
69 next-level-cache = <&L2_0>;
71 operating-points-v2 = <&cpu_opp_table>;
74 L2_0: l2-cache {
76 cache-level = <2>;
77 cache-unified;
83 compatible = "qcom,scm-ipq5332", "qcom,scm";
84 qcom,dload-mode = <&tcsr 0x6100>;
91 reg = <0x0 0x40000000 0x0 0x0>;
94 cpu_opp_table: opp-table-cpu {
95 compatible = "operating-points-v2-kryo-cpu";
96 opp-shared;
97 nvmem-cells = <&cpu_speed_bin>;
99 opp-1100000000 {
100 opp-hz = /bits/ 64 <1100000000>;
101 opp-supported-hw = <0x7>;
102 clock-latency-ns = <200000>;
105 opp-1500000000 {
106 opp-hz = /bits/ 64 <1500000000>;
107 opp-supported-hw = <0x3>;
108 clock-latency-ns = <200000>;
113 compatible = "arm,cortex-a53-pmu";
118 compatible = "arm,psci-1.0";
122 reserved-memory {
123 #address-cells = <2>;
124 #size-cells = <2>;
128 reg = <0x0 0x4a100000 0x0 0x400000>;
129 no-map;
133 reg = <0x0 0x4a500000 0x0 0x100000>;
134 no-map;
138 reg = <0x0 0x4a600000 0x0 0x200000>;
139 no-map;
144 reg = <0x0 0x4a800000 0x0 0x100000>;
145 no-map;
152 compatible = "simple-bus";
153 #address-cells = <1>;
154 #size-cells = <1>;
158 compatible = "qcom,ipq5332-usb-hsphy";
159 reg = <0x0007b000 0x12c>;
165 #phy-cells = <0>;
171 compatible = "qcom,ipq5332-qfprom", "qcom,qfprom";
172 reg = <0x000a4000 0x721>;
173 #address-cells = <1>;
174 #size-cells = <1>;
176 cpu_speed_bin: cpu-speed-bin@1d {
177 reg = <0x1d 0x2>;
183 compatible = "qcom,prng-ee";
184 reg = <0x000e3000 0x1000>;
186 clock-names = "core";
190 compatible = "qcom,ipq5332-tlmm";
191 reg = <0x01000000 0x300000>;
193 gpio-controller;
194 #gpio-cells = <2>;
195 gpio-ranges = <&tlmm 0 0 53>;
196 interrupt-controller;
197 #interrupt-cells = <2>;
199 serial_0_pins: serial0-state {
202 drive-strength = <8>;
203 bias-pull-up;
207 gcc: clock-controller@1800000 {
208 compatible = "qcom,ipq5332-gcc";
209 reg = <0x01800000 0x80000>;
210 #clock-cells = <1>;
211 #reset-cells = <1>;
212 #interconnect-cells = <1>;
221 compatible = "qcom,tcsr-mutex";
222 reg = <0x01905000 0x20000>;
223 #hwlock-cells = <1>;
226 tcsr: syscon@1937000 { label
227 compatible = "qcom,tcsr-ipq5332", "syscon";
228 reg = <0x01937000 0x21000>;
232 compatible = "qcom,ipq5332-sdhci", "qcom,sdhci-msm-v5";
233 reg = <0x07804000 0x1000>, <0x07805000 0x1000>;
237 interrupt-names = "hc_irq", "pwr_irq";
242 clock-names = "iface", "core", "xo";
246 blsp_dma: dma-controller@7884000 {
247 compatible = "qcom,bam-v1.7.0";
248 reg = <0x07884000 0x1d000>;
251 clock-names = "bam_clk";
252 #dma-cells = <1>;
257 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
258 reg = <0x078af000 0x200>;
262 clock-names = "core", "iface";
267 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
268 reg = <0x078b0000 0x200>;
272 clock-names = "core", "iface";
274 dma-names = "tx", "rx";
279 compatible = "qcom,spi-qup-v2.2.1";
280 reg = <0x078b5000 0x600>;
281 #address-cells = <1>;
282 #size-cells = <0>;
286 clock-names = "core", "iface";
288 dma-names = "tx", "rx";
293 compatible = "qcom,i2c-qup-v2.2.1";
294 reg = <0x078b6000 0x600>;
295 #address-cells = <1>;
296 #size-cells = <0>;
300 clock-names = "core", "iface";
302 dma-names = "tx", "rx";
307 compatible = "qcom,spi-qup-v2.2.1";
308 reg = <0x078b7000 0x600>;
309 #address-cells = <1>;
310 #size-cells = <0>;
314 clock-names = "core", "iface";
316 dma-names = "tx", "rx";
321 compatible = "qcom,ipq5332-dwc3", "qcom,dwc3";
322 reg = <0x08af8800 0x400>;
327 interrupt-names = "pwr_event",
334 clock-names = "core",
340 qcom,select-utmi-as-pipe-clk;
342 #address-cells = <1>;
343 #size-cells = <1>;
347 interconnect-names = "usb-ddr", "apps-usb";
353 reg = <0x08a00000 0xe000>;
355 clock-names = "ref";
357 phy-names = "usb2-phy";
359 tx-fifo-resize;
360 snps,is-utmi-l1-suspend;
361 snps,hird-threshold = /bits/ 8 <0x0>;
367 intc: interrupt-controller@b000000 {
368 compatible = "qcom,msm-qgic2";
369 reg = <0x0b000000 0x1000>, /* GICD */
374 interrupt-controller;
375 #interrupt-cells = <3>;
376 #address-cells = <1>;
377 #size-cells = <1>;
381 compatible = "arm,gic-v2m-frame";
382 reg = <0x00000000 0xffd>;
383 msi-controller;
387 compatible = "arm,gic-v2m-frame";
388 reg = <0x00001000 0xffd>;
389 msi-controller;
393 compatible = "arm,gic-v2m-frame";
394 reg = <0x00002000 0xffd>;
395 msi-controller;
400 compatible = "qcom,apss-wdt-ipq5332", "qcom,kpss-wdt";
401 reg = <0x0b017000 0x1000>;
404 timeout-sec = <30>;
408 compatible = "qcom,ipq5332-apcs-apps-global",
409 "qcom,ipq6018-apcs-apps-global";
410 reg = <0x0b111000 0x1000>;
411 #clock-cells = <1>;
413 clock-names = "pll", "xo", "gpll0";
414 #mbox-cells = <1>;
418 compatible = "qcom,ipq5332-a53pll";
419 reg = <0x0b116000 0x40>;
420 #clock-cells = <0>;
422 clock-names = "xo";
426 compatible = "arm,armv7-timer-mem";
427 reg = <0x0b120000 0x1000>;
428 #address-cells = <1>;
429 #size-cells = <1>;
433 reg = <0x0b121000 0x1000>,
437 frame-number = <0>;
441 reg = <0x0b123000 0x1000>;
443 frame-number = <1>;
448 reg = <0x0b124000 0x1000>;
450 frame-number = <2>;
455 reg = <0x0b125000 0x1000>;
457 frame-number = <3>;
462 reg = <0x0b126000 0x1000>;
464 frame-number = <4>;
469 reg = <0x0b127000 0x1000>;
471 frame-number = <5>;
476 reg = <0x0b128000 0x1000>;
478 frame-number = <6>;
485 compatible = "arm,armv8-timer";