Lines Matching refs:TEGRA194_CLK_PLLA_OUT0

250 					assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
264 					assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
278 					assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
292 					assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
306 					assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
320 					assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
425 					assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
438 					assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
451 					assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
464 					assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
477 					assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
490 					assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
3119 			 <&bpmp TEGRA194_CLK_PLLA_OUT0>;
3122 				  <&bpmp TEGRA194_CLK_PLLA_OUT0>,
3126 					 <&bpmp TEGRA194_CLK_PLLA_OUT0>;