Lines Matching +full:cpu +full:- +full:bpmp +full:- +full:rx
1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra194-clock.h>
3 #include <dt-bindings/gpio/tegra194-gpio.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/mailbox/tegra186-hsp.h>
6 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
7 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
8 #include <dt-bindings/power/tegra194-powergate.h>
9 #include <dt-bindings/reset/tegra194-reset.h>
10 #include <dt-bindings/thermal/tegra194-bpmp-thermal.h>
11 #include <dt-bindings/memory/tegra194-mc.h>
15 interrupt-parent = <&gic>;
16 #address-cells = <2>;
17 #size-cells = <2>;
21 compatible = "simple-bus";
23 #address-cells = <2>;
24 #size-cells = <2>;
28 compatible = "nvidia,tegra194-misc";
34 compatible = "nvidia,tegra194-gpio";
35 reg-names = "security", "gpio";
86 #interrupt-cells = <2>;
87 interrupt-controller;
88 #gpio-cells = <2>;
89 gpio-controller;
90 gpio-ranges = <&pinmux 0 0 169>;
93 cbb-noc@2300000 {
94 compatible = "nvidia,tegra194-cbb-noc";
104 compatible = "nvidia,tegra194-axi2apb";
115 compatible = "nvidia,tegra194-pinmux";
119 pex_clkreq_c5_bi_dir_state: pinmux-pex-clkreq-c5-bi-dir {
123 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
124 nvidia,io-hv = <TEGRA_PIN_ENABLE>;
130 pex_rst_c5_out_state: pinmux-pex-rst-c5-out {
134 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
135 nvidia,io-hv = <TEGRA_PIN_ENABLE>;
143 compatible = "nvidia,tegra194-eqos",
144 "nvidia,tegra186-eqos",
145 "snps,dwc-qos-ethernet-4.10";
148 clocks = <&bpmp TEGRA194_CLK_AXI_CBB>,
149 <&bpmp TEGRA194_CLK_EQOS_AXI>,
150 <&bpmp TEGRA194_CLK_EQOS_RX>,
151 <&bpmp TEGRA194_CLK_EQOS_TX>,
152 <&bpmp TEGRA194_CLK_EQOS_PTP_REF>;
153 clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref";
154 resets = <&bpmp TEGRA194_RESET_EQOS>;
155 reset-names = "eqos";
158 interconnect-names = "dma-mem", "write";
162 snps,write-requests = <1>;
163 snps,read-requests = <3>;
164 snps,burst-map = <0x7>;
169 gpcdma: dma-controller@2600000 {
170 compatible = "nvidia,tegra194-gpcdma",
171 "nvidia,tegra186-gpcdma";
173 resets = <&bpmp TEGRA194_RESET_GPCDMA>;
174 reset-names = "gpcdma";
207 #dma-cells = <1>;
209 dma-coherent;
210 dma-channel-mask = <0xfffffffe>;
215 compatible = "nvidia,tegra194-aconnect",
216 "nvidia,tegra210-aconnect";
217 clocks = <&bpmp TEGRA194_CLK_APE>,
218 <&bpmp TEGRA194_CLK_APB2APE>;
219 clock-names = "ape", "apb2ape";
220 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_AUD>;
223 #address-cells = <2>;
224 #size-cells = <2>;
228 compatible = "nvidia,tegra194-ahub",
229 "nvidia,tegra186-ahub";
231 clocks = <&bpmp TEGRA194_CLK_AHUB>;
232 clock-names = "ahub";
233 assigned-clocks = <&bpmp TEGRA194_CLK_AHUB>;
234 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLP_OUT0>;
235 assigned-clock-rates = <81600000>;
238 #address-cells = <2>;
239 #size-cells = <2>;
243 compatible = "nvidia,tegra194-i2s",
244 "nvidia,tegra210-i2s";
246 clocks = <&bpmp TEGRA194_CLK_I2S1>,
247 <&bpmp TEGRA194_CLK_I2S1_SYNC_INPUT>;
248 clock-names = "i2s", "sync_input";
249 assigned-clocks = <&bpmp TEGRA194_CLK_I2S1>;
250 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
251 assigned-clock-rates = <1536000>;
252 sound-name-prefix = "I2S1";
257 compatible = "nvidia,tegra194-i2s",
258 "nvidia,tegra210-i2s";
260 clocks = <&bpmp TEGRA194_CLK_I2S2>,
261 <&bpmp TEGRA194_CLK_I2S2_SYNC_INPUT>;
262 clock-names = "i2s", "sync_input";
263 assigned-clocks = <&bpmp TEGRA194_CLK_I2S2>;
264 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
265 assigned-clock-rates = <1536000>;
266 sound-name-prefix = "I2S2";
271 compatible = "nvidia,tegra194-i2s",
272 "nvidia,tegra210-i2s";
274 clocks = <&bpmp TEGRA194_CLK_I2S3>,
275 <&bpmp TEGRA194_CLK_I2S3_SYNC_INPUT>;
276 clock-names = "i2s", "sync_input";
277 assigned-clocks = <&bpmp TEGRA194_CLK_I2S3>;
278 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
279 assigned-clock-rates = <1536000>;
280 sound-name-prefix = "I2S3";
285 compatible = "nvidia,tegra194-i2s",
286 "nvidia,tegra210-i2s";
288 clocks = <&bpmp TEGRA194_CLK_I2S4>,
289 <&bpmp TEGRA194_CLK_I2S4_SYNC_INPUT>;
290 clock-names = "i2s", "sync_input";
291 assigned-clocks = <&bpmp TEGRA194_CLK_I2S4>;
292 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
293 assigned-clock-rates = <1536000>;
294 sound-name-prefix = "I2S4";
299 compatible = "nvidia,tegra194-i2s",
300 "nvidia,tegra210-i2s";
302 clocks = <&bpmp TEGRA194_CLK_I2S5>,
303 <&bpmp TEGRA194_CLK_I2S5_SYNC_INPUT>;
304 clock-names = "i2s", "sync_input";
305 assigned-clocks = <&bpmp TEGRA194_CLK_I2S5>;
306 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
307 assigned-clock-rates = <1536000>;
308 sound-name-prefix = "I2S5";
313 compatible = "nvidia,tegra194-i2s",
314 "nvidia,tegra210-i2s";
316 clocks = <&bpmp TEGRA194_CLK_I2S6>,
317 <&bpmp TEGRA194_CLK_I2S6_SYNC_INPUT>;
318 clock-names = "i2s", "sync_input";
319 assigned-clocks = <&bpmp TEGRA194_CLK_I2S6>;
320 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
321 assigned-clock-rates = <1536000>;
322 sound-name-prefix = "I2S6";
327 compatible = "nvidia,tegra194-sfc",
328 "nvidia,tegra210-sfc";
330 sound-name-prefix = "SFC1";
335 compatible = "nvidia,tegra194-sfc",
336 "nvidia,tegra210-sfc";
338 sound-name-prefix = "SFC2";
343 compatible = "nvidia,tegra194-sfc",
344 "nvidia,tegra210-sfc";
346 sound-name-prefix = "SFC3";
351 compatible = "nvidia,tegra194-sfc",
352 "nvidia,tegra210-sfc";
354 sound-name-prefix = "SFC4";
359 compatible = "nvidia,tegra194-amx";
361 sound-name-prefix = "AMX1";
366 compatible = "nvidia,tegra194-amx";
368 sound-name-prefix = "AMX2";
373 compatible = "nvidia,tegra194-amx";
375 sound-name-prefix = "AMX3";
380 compatible = "nvidia,tegra194-amx";
382 sound-name-prefix = "AMX4";
387 compatible = "nvidia,tegra194-adx",
388 "nvidia,tegra210-adx";
390 sound-name-prefix = "ADX1";
395 compatible = "nvidia,tegra194-adx",
396 "nvidia,tegra210-adx";
398 sound-name-prefix = "ADX2";
403 compatible = "nvidia,tegra194-adx",
404 "nvidia,tegra210-adx";
406 sound-name-prefix = "ADX3";
411 compatible = "nvidia,tegra194-adx",
412 "nvidia,tegra210-adx";
414 sound-name-prefix = "ADX4";
419 compatible = "nvidia,tegra194-dmic",
420 "nvidia,tegra210-dmic";
422 clocks = <&bpmp TEGRA194_CLK_DMIC1>;
423 clock-names = "dmic";
424 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC1>;
425 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
426 assigned-clock-rates = <3072000>;
427 sound-name-prefix = "DMIC1";
432 compatible = "nvidia,tegra194-dmic",
433 "nvidia,tegra210-dmic";
435 clocks = <&bpmp TEGRA194_CLK_DMIC2>;
436 clock-names = "dmic";
437 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC2>;
438 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
439 assigned-clock-rates = <3072000>;
440 sound-name-prefix = "DMIC2";
445 compatible = "nvidia,tegra194-dmic",
446 "nvidia,tegra210-dmic";
448 clocks = <&bpmp TEGRA194_CLK_DMIC3>;
449 clock-names = "dmic";
450 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC3>;
451 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
452 assigned-clock-rates = <3072000>;
453 sound-name-prefix = "DMIC3";
458 compatible = "nvidia,tegra194-dmic",
459 "nvidia,tegra210-dmic";
461 clocks = <&bpmp TEGRA194_CLK_DMIC4>;
462 clock-names = "dmic";
463 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC4>;
464 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
465 assigned-clock-rates = <3072000>;
466 sound-name-prefix = "DMIC4";
471 compatible = "nvidia,tegra194-dspk",
472 "nvidia,tegra186-dspk";
474 clocks = <&bpmp TEGRA194_CLK_DSPK1>;
475 clock-names = "dspk";
476 assigned-clocks = <&bpmp TEGRA194_CLK_DSPK1>;
477 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
478 assigned-clock-rates = <12288000>;
479 sound-name-prefix = "DSPK1";
484 compatible = "nvidia,tegra194-dspk",
485 "nvidia,tegra186-dspk";
487 clocks = <&bpmp TEGRA194_CLK_DSPK2>;
488 clock-names = "dspk";
489 assigned-clocks = <&bpmp TEGRA194_CLK_DSPK2>;
490 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
491 assigned-clock-rates = <12288000>;
492 sound-name-prefix = "DSPK2";
496 tegra_ope1: processing-engine@2908000 {
497 compatible = "nvidia,tegra194-ope",
498 "nvidia,tegra210-ope";
500 sound-name-prefix = "OPE1";
503 #address-cells = <2>;
504 #size-cells = <2>;
508 compatible = "nvidia,tegra194-peq",
509 "nvidia,tegra210-peq";
513 dynamic-range-compressor@2908200 {
514 compatible = "nvidia,tegra194-mbdrc",
515 "nvidia,tegra210-mbdrc";
521 compatible = "nvidia,tegra194-mvc",
522 "nvidia,tegra210-mvc";
524 sound-name-prefix = "MVC1";
529 compatible = "nvidia,tegra194-mvc",
530 "nvidia,tegra210-mvc";
532 sound-name-prefix = "MVC2";
537 compatible = "nvidia,tegra194-amixer",
538 "nvidia,tegra210-amixer";
540 sound-name-prefix = "MIXER1";
545 compatible = "nvidia,tegra194-admaif",
546 "nvidia,tegra186-admaif";
568 dma-names = "rx1", "tx1",
591 interconnect-names = "dma-mem", "write";
596 compatible = "nvidia,tegra194-asrc",
597 "nvidia,tegra186-asrc";
599 sound-name-prefix = "ASRC1";
604 adma: dma-controller@2930000 {
605 compatible = "nvidia,tegra194-adma",
606 "nvidia,tegra186-adma";
608 interrupt-parent = <&agic>;
641 #dma-cells = <1>;
642 clocks = <&bpmp TEGRA194_CLK_AHUB>;
643 clock-names = "d_audio";
647 agic: interrupt-controller@2a40000 {
648 compatible = "nvidia,tegra194-agic",
649 "nvidia,tegra210-agic";
650 #interrupt-cells = <3>;
651 interrupt-controller;
657 clocks = <&bpmp TEGRA194_CLK_APE>;
658 clock-names = "clk";
663 mc: memory-controller@2c00000 {
664 compatible = "nvidia,tegra194-mc";
665 reg = <0x0 0x02c00000 0x0 0x10000>, /* MC-SID */
683 reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3",
687 #interconnect-cells = <1>;
690 #address-cells = <2>;
691 #size-cells = <2>;
711 dma-ranges = <0x0 0x0 0x0 0x0 0x80 0x0>;
713 emc: external-memory-controller@2c60000 {
714 compatible = "nvidia,tegra194-emc";
718 clocks = <&bpmp TEGRA194_CLK_EMC>;
719 clock-names = "emc";
721 #interconnect-cells = <0>;
723 nvidia,bpmp = <&bpmp>;
728 compatible = "nvidia,tegra186-timer";
744 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
746 reg-shift = <2>;
748 clocks = <&bpmp TEGRA194_CLK_UARTA>;
749 resets = <&bpmp TEGRA194_RESET_UARTA>;
754 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
756 reg-shift = <2>;
758 clocks = <&bpmp TEGRA194_CLK_UARTB>;
759 resets = <&bpmp TEGRA194_RESET_UARTB>;
764 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
766 reg-shift = <2>;
768 clocks = <&bpmp TEGRA194_CLK_UARTD>;
769 clock-names = "serial";
770 resets = <&bpmp TEGRA194_RESET_UARTD>;
771 reset-names = "serial";
776 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
778 reg-shift = <2>;
780 clocks = <&bpmp TEGRA194_CLK_UARTE>;
781 clock-names = "serial";
782 resets = <&bpmp TEGRA194_RESET_UARTE>;
783 reset-names = "serial";
788 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
790 reg-shift = <2>;
792 clocks = <&bpmp TEGRA194_CLK_UARTF>;
793 clock-names = "serial";
794 resets = <&bpmp TEGRA194_RESET_UARTF>;
795 reset-names = "serial";
800 compatible = "nvidia,tegra194-i2c";
803 #address-cells = <1>;
804 #size-cells = <0>;
805 clocks = <&bpmp TEGRA194_CLK_I2C1>;
806 clock-names = "div-clk";
807 resets = <&bpmp TEGRA194_RESET_I2C1>;
808 reset-names = "i2c";
810 dma-names = "rx", "tx";
815 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
817 reg-shift = <2>;
819 clocks = <&bpmp TEGRA194_CLK_UARTH>;
820 clock-names = "serial";
821 resets = <&bpmp TEGRA194_RESET_UARTH>;
822 reset-names = "serial";
827 compatible = "nvidia,tegra194-i2c";
830 #address-cells = <1>;
831 #size-cells = <0>;
832 clocks = <&bpmp TEGRA194_CLK_I2C3>;
833 clock-names = "div-clk";
834 resets = <&bpmp TEGRA194_RESET_I2C3>;
835 reset-names = "i2c";
837 dma-names = "rx", "tx";
843 compatible = "nvidia,tegra194-i2c";
846 #address-cells = <1>;
847 #size-cells = <0>;
848 clocks = <&bpmp TEGRA194_CLK_I2C4>;
849 clock-names = "div-clk";
850 resets = <&bpmp TEGRA194_RESET_I2C4>;
851 reset-names = "i2c";
852 pinctrl-0 = <&state_dpaux1_i2c>;
853 pinctrl-1 = <&state_dpaux1_off>;
854 pinctrl-names = "default", "idle";
856 dma-names = "rx", "tx";
862 compatible = "nvidia,tegra194-i2c";
865 #address-cells = <1>;
866 #size-cells = <0>;
867 clocks = <&bpmp TEGRA194_CLK_I2C6>;
868 clock-names = "div-clk";
869 resets = <&bpmp TEGRA194_RESET_I2C6>;
870 reset-names = "i2c";
871 pinctrl-0 = <&state_dpaux0_i2c>;
872 pinctrl-1 = <&state_dpaux0_off>;
873 pinctrl-names = "default", "idle";
875 dma-names = "rx", "tx";
881 compatible = "nvidia,tegra194-i2c";
884 #address-cells = <1>;
885 #size-cells = <0>;
886 clocks = <&bpmp TEGRA194_CLK_I2C7>;
887 clock-names = "div-clk";
888 resets = <&bpmp TEGRA194_RESET_I2C7>;
889 reset-names = "i2c";
890 pinctrl-0 = <&state_dpaux2_i2c>;
891 pinctrl-1 = <&state_dpaux2_off>;
892 pinctrl-names = "default", "idle";
894 dma-names = "rx", "tx";
900 compatible = "nvidia,tegra194-i2c";
903 #address-cells = <1>;
904 #size-cells = <0>;
905 clocks = <&bpmp TEGRA194_CLK_I2C9>;
906 clock-names = "div-clk";
907 resets = <&bpmp TEGRA194_RESET_I2C9>;
908 reset-names = "i2c";
909 pinctrl-0 = <&state_dpaux3_i2c>;
910 pinctrl-1 = <&state_dpaux3_off>;
911 pinctrl-names = "default", "idle";
913 dma-names = "rx", "tx";
918 compatible = "nvidia,tegra194-qspi";
921 #address-cells = <1>;
922 #size-cells = <0>;
923 clocks = <&bpmp TEGRA194_CLK_QSPI0>,
924 <&bpmp TEGRA194_CLK_QSPI0_PM>;
925 clock-names = "qspi", "qspi_out";
926 resets = <&bpmp TEGRA194_RESET_QSPI0>;
931 compatible = "nvidia,tegra194-pwm",
932 "nvidia,tegra186-pwm";
934 clocks = <&bpmp TEGRA194_CLK_PWM1>;
935 resets = <&bpmp TEGRA194_RESET_PWM1>;
936 reset-names = "pwm";
938 #pwm-cells = <2>;
942 compatible = "nvidia,tegra194-pwm",
943 "nvidia,tegra186-pwm";
945 clocks = <&bpmp TEGRA194_CLK_PWM2>;
946 resets = <&bpmp TEGRA194_RESET_PWM2>;
947 reset-names = "pwm";
949 #pwm-cells = <2>;
953 compatible = "nvidia,tegra194-pwm",
954 "nvidia,tegra186-pwm";
956 clocks = <&bpmp TEGRA194_CLK_PWM3>;
957 resets = <&bpmp TEGRA194_RESET_PWM3>;
958 reset-names = "pwm";
960 #pwm-cells = <2>;
964 compatible = "nvidia,tegra194-pwm",
965 "nvidia,tegra186-pwm";
967 clocks = <&bpmp TEGRA194_CLK_PWM5>;
968 resets = <&bpmp TEGRA194_RESET_PWM5>;
969 reset-names = "pwm";
971 #pwm-cells = <2>;
975 compatible = "nvidia,tegra194-pwm",
976 "nvidia,tegra186-pwm";
978 clocks = <&bpmp TEGRA194_CLK_PWM6>;
979 resets = <&bpmp TEGRA194_RESET_PWM6>;
980 reset-names = "pwm";
982 #pwm-cells = <2>;
986 compatible = "nvidia,tegra194-pwm",
987 "nvidia,tegra186-pwm";
989 clocks = <&bpmp TEGRA194_CLK_PWM7>;
990 resets = <&bpmp TEGRA194_RESET_PWM7>;
991 reset-names = "pwm";
993 #pwm-cells = <2>;
997 compatible = "nvidia,tegra194-pwm",
998 "nvidia,tegra186-pwm";
1000 clocks = <&bpmp TEGRA194_CLK_PWM8>;
1001 resets = <&bpmp TEGRA194_RESET_PWM8>;
1002 reset-names = "pwm";
1004 #pwm-cells = <2>;
1008 compatible = "nvidia,tegra194-qspi";
1011 #address-cells = <1>;
1012 #size-cells = <0>;
1013 clocks = <&bpmp TEGRA194_CLK_QSPI1>,
1014 <&bpmp TEGRA194_CLK_QSPI1_PM>;
1015 clock-names = "qspi", "qspi_out";
1016 resets = <&bpmp TEGRA194_RESET_QSPI1>;
1021 compatible = "nvidia,tegra194-sdhci";
1024 clocks = <&bpmp TEGRA194_CLK_SDMMC1>,
1025 <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>;
1026 clock-names = "sdhci", "tmclk";
1027 assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC1>,
1028 <&bpmp TEGRA194_CLK_PLLC4_MUXED>;
1029 assigned-clock-parents =
1030 <&bpmp TEGRA194_CLK_PLLC4_MUXED>,
1031 <&bpmp TEGRA194_CLK_PLLC4_VCO_DIV2>;
1032 resets = <&bpmp TEGRA194_RESET_SDMMC1>;
1033 reset-names = "sdhci";
1036 interconnect-names = "dma-mem", "write";
1038 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
1039 pinctrl-0 = <&sdmmc1_3v3>;
1040 pinctrl-1 = <&sdmmc1_1v8>;
1041 nvidia,pad-autocal-pull-up-offset-3v3-timeout =
1043 nvidia,pad-autocal-pull-down-offset-3v3-timeout =
1045 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>;
1046 nvidia,pad-autocal-pull-down-offset-1v8-timeout =
1048 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>;
1049 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>;
1050 nvidia,default-tap = <0x9>;
1051 nvidia,default-trim = <0x5>;
1052 sd-uhs-sdr25;
1053 sd-uhs-sdr50;
1054 sd-uhs-ddr50;
1055 sd-uhs-sdr104;
1060 compatible = "nvidia,tegra194-sdhci";
1063 clocks = <&bpmp TEGRA194_CLK_SDMMC3>,
1064 <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>;
1065 clock-names = "sdhci", "tmclk";
1066 assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC3>,
1067 <&bpmp TEGRA194_CLK_PLLC4_MUXED>;
1068 assigned-clock-parents =
1069 <&bpmp TEGRA194_CLK_PLLC4_MUXED>,
1070 <&bpmp TEGRA194_CLK_PLLC4_VCO_DIV2>;
1071 resets = <&bpmp TEGRA194_RESET_SDMMC3>;
1072 reset-names = "sdhci";
1075 interconnect-names = "dma-mem", "write";
1077 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
1078 pinctrl-0 = <&sdmmc3_3v3>;
1079 pinctrl-1 = <&sdmmc3_1v8>;
1080 nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>;
1081 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>;
1082 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
1083 nvidia,pad-autocal-pull-down-offset-3v3-timeout =
1085 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>;
1086 nvidia,pad-autocal-pull-down-offset-1v8-timeout =
1088 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>;
1089 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>;
1090 nvidia,default-tap = <0x9>;
1091 nvidia,default-trim = <0x5>;
1092 sd-uhs-sdr25;
1093 sd-uhs-sdr50;
1094 sd-uhs-ddr50;
1095 sd-uhs-sdr104;
1100 compatible = "nvidia,tegra194-sdhci";
1103 clocks = <&bpmp TEGRA194_CLK_SDMMC4>,
1104 <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>;
1105 clock-names = "sdhci", "tmclk";
1106 assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC4>,
1107 <&bpmp TEGRA194_CLK_PLLC4>;
1108 assigned-clock-parents =
1109 <&bpmp TEGRA194_CLK_PLLC4>;
1110 resets = <&bpmp TEGRA194_RESET_SDMMC4>;
1111 reset-names = "sdhci";
1114 interconnect-names = "dma-mem", "write";
1116 nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>;
1117 nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>;
1118 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>;
1119 nvidia,pad-autocal-pull-down-offset-1v8-timeout =
1121 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>;
1122 nvidia,pad-autocal-pull-down-offset-3v3-timeout =
1124 nvidia,default-tap = <0x8>;
1125 nvidia,default-trim = <0x14>;
1126 nvidia,dqs-trim = <40>;
1127 cap-mmc-highspeed;
1128 mmc-ddr-1_8v;
1129 mmc-hs200-1_8v;
1130 mmc-hs400-1_8v;
1131 mmc-hs400-enhanced-strobe;
1132 supports-cqe;
1137 compatible = "nvidia,tegra194-hda";
1140 clocks = <&bpmp TEGRA194_CLK_HDA>,
1141 <&bpmp TEGRA194_CLK_HDA2HDMICODEC>,
1142 <&bpmp TEGRA194_CLK_HDA2CODEC_2X>;
1143 clock-names = "hda", "hda2hdmi", "hda2codec_2x";
1144 resets = <&bpmp TEGRA194_RESET_HDA>,
1145 <&bpmp TEGRA194_RESET_HDA2HDMICODEC>;
1146 reset-names = "hda", "hda2hdmi";
1147 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1150 interconnect-names = "dma-mem", "write";
1156 compatible = "nvidia,tegra194-xusb-padctl";
1159 reg-names = "padctl", "ao";
1162 resets = <&bpmp TEGRA194_RESET_XUSB_PADCTL>;
1163 reset-names = "padctl";
1169 clocks = <&bpmp TEGRA194_CLK_USB2_TRK>;
1170 clock-names = "trk";
1173 usb2-0 {
1176 #phy-cells = <0>;
1179 usb2-1 {
1182 #phy-cells = <0>;
1185 usb2-2 {
1188 #phy-cells = <0>;
1191 usb2-3 {
1194 #phy-cells = <0>;
1201 usb3-0 {
1204 #phy-cells = <0>;
1207 usb3-1 {
1210 #phy-cells = <0>;
1213 usb3-2 {
1216 #phy-cells = <0>;
1219 usb3-3 {
1222 #phy-cells = <0>;
1229 usb2-0 {
1233 usb2-1 {
1237 usb2-2 {
1241 usb2-3 {
1245 usb3-0 {
1249 usb3-1 {
1253 usb3-2 {
1257 usb3-3 {
1264 compatible = "nvidia,tegra194-xudc";
1267 reg-names = "base", "fpci";
1269 clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_DEV>,
1270 <&bpmp TEGRA194_CLK_XUSB_CORE_SS>,
1271 <&bpmp TEGRA194_CLK_XUSB_SS>,
1272 <&bpmp TEGRA194_CLK_XUSB_FS>;
1273 clock-names = "dev", "ss", "ss_src", "fs_src";
1276 interconnect-names = "dma-mem", "write";
1278 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBB>,
1279 <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>;
1280 power-domain-names = "dev", "ss";
1281 nvidia,xusb-padctl = <&xusb_padctl>;
1282 dma-coherent;
1287 compatible = "nvidia,tegra194-xusb";
1290 reg-names = "hcd", "fpci";
1295 clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_HOST>,
1296 <&bpmp TEGRA194_CLK_XUSB_FALCON>,
1297 <&bpmp TEGRA194_CLK_XUSB_CORE_SS>,
1298 <&bpmp TEGRA194_CLK_XUSB_SS>,
1299 <&bpmp TEGRA194_CLK_CLK_M>,
1300 <&bpmp TEGRA194_CLK_XUSB_FS>,
1301 <&bpmp TEGRA194_CLK_UTMIPLL>,
1302 <&bpmp TEGRA194_CLK_CLK_M>,
1303 <&bpmp TEGRA194_CLK_PLLE>;
1304 clock-names = "xusb_host", "xusb_falcon_src",
1310 interconnect-names = "dma-mem", "write";
1313 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBC>,
1314 <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>;
1315 power-domain-names = "xusb_host", "xusb_ss";
1317 nvidia,xusb-padctl = <&xusb_padctl>;
1322 compatible = "nvidia,tegra194-efuse";
1324 clocks = <&bpmp TEGRA194_CLK_FUSE>;
1325 clock-names = "fuse";
1328 gic: interrupt-controller@3881000 {
1329 compatible = "arm,gic-400";
1330 #interrupt-cells = <3>;
1331 interrupt-controller;
1338 interrupt-parent = <&gic>;
1342 compatible = "nvidia,tegra194-cec";
1345 clocks = <&bpmp TEGRA194_CLK_CEC>;
1346 clock-names = "cec";
1350 hte_lic: hardware-timestamp@3aa0000 {
1351 compatible = "nvidia,tegra194-gte-lic";
1354 nvidia,int-threshold = <1>;
1356 #timestamp-cells = <1>;
1361 compatible = "nvidia,tegra194-hsp";
1372 interrupt-names = "doorbell", "shared0", "shared1", "shared2",
1375 #mbox-cells = <2>;
1379 compatible = "nvidia,tegra194-p2u";
1381 reg-names = "ctl";
1383 #phy-cells = <0>;
1387 compatible = "nvidia,tegra194-p2u";
1389 reg-names = "ctl";
1391 #phy-cells = <0>;
1395 compatible = "nvidia,tegra194-p2u";
1397 reg-names = "ctl";
1399 #phy-cells = <0>;
1403 compatible = "nvidia,tegra194-p2u";
1405 reg-names = "ctl";
1407 #phy-cells = <0>;
1411 compatible = "nvidia,tegra194-p2u";
1413 reg-names = "ctl";
1415 #phy-cells = <0>;
1419 compatible = "nvidia,tegra194-p2u";
1421 reg-names = "ctl";
1423 #phy-cells = <0>;
1427 compatible = "nvidia,tegra194-p2u";
1429 reg-names = "ctl";
1431 #phy-cells = <0>;
1435 compatible = "nvidia,tegra194-p2u";
1437 reg-names = "ctl";
1439 #phy-cells = <0>;
1443 compatible = "nvidia,tegra194-p2u";
1445 reg-names = "ctl";
1447 #phy-cells = <0>;
1451 compatible = "nvidia,tegra194-p2u";
1453 reg-names = "ctl";
1455 #phy-cells = <0>;
1459 compatible = "nvidia,tegra194-p2u";
1461 reg-names = "ctl";
1463 #phy-cells = <0>;
1467 compatible = "nvidia,tegra194-p2u";
1469 reg-names = "ctl";
1471 #phy-cells = <0>;
1475 compatible = "nvidia,tegra194-p2u";
1477 reg-names = "ctl";
1479 #phy-cells = <0>;
1483 compatible = "nvidia,tegra194-p2u";
1485 reg-names = "ctl";
1487 #phy-cells = <0>;
1491 compatible = "nvidia,tegra194-p2u";
1493 reg-names = "ctl";
1495 #phy-cells = <0>;
1499 compatible = "nvidia,tegra194-p2u";
1501 reg-names = "ctl";
1503 #phy-cells = <0>;
1507 compatible = "nvidia,tegra194-p2u";
1509 reg-names = "ctl";
1511 #phy-cells = <0>;
1515 compatible = "nvidia,tegra194-p2u";
1517 reg-names = "ctl";
1519 #phy-cells = <0>;
1523 compatible = "nvidia,tegra194-p2u";
1525 reg-names = "ctl";
1527 #phy-cells = <0>;
1531 compatible = "nvidia,tegra194-p2u";
1533 reg-names = "ctl";
1535 #phy-cells = <0>;
1538 sce-noc@b600000 {
1539 compatible = "nvidia,tegra194-sce-noc";
1548 rce-noc@be00000 {
1549 compatible = "nvidia,tegra194-rce-noc";
1559 compatible = "nvidia,tegra194-hsp";
1569 interrupt-names = "shared1", "shared2", "shared3", "shared4";
1570 #mbox-cells = <2>;
1573 hte_aon: hardware-timestamp@c1e0000 {
1574 compatible = "nvidia,tegra194-gte-aon";
1577 nvidia,int-threshold = <1>;
1579 #timestamp-cells = <1>;
1584 compatible = "nvidia,tegra194-i2c";
1587 #address-cells = <1>;
1588 #size-cells = <0>;
1589 clocks = <&bpmp TEGRA194_CLK_I2C2>;
1590 clock-names = "div-clk";
1591 resets = <&bpmp TEGRA194_RESET_I2C2>;
1592 reset-names = "i2c";
1594 dma-names = "rx", "tx";
1599 compatible = "nvidia,tegra194-i2c";
1602 #address-cells = <1>;
1603 #size-cells = <0>;
1604 clocks = <&bpmp TEGRA194_CLK_I2C8>;
1605 clock-names = "div-clk";
1606 resets = <&bpmp TEGRA194_RESET_I2C8>;
1607 reset-names = "i2c";
1609 dma-names = "rx", "tx";
1614 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
1616 reg-shift = <2>;
1618 clocks = <&bpmp TEGRA194_CLK_UARTC>;
1619 clock-names = "serial";
1620 resets = <&bpmp TEGRA194_RESET_UARTC>;
1621 reset-names = "serial";
1626 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
1628 reg-shift = <2>;
1630 clocks = <&bpmp TEGRA194_CLK_UARTG>;
1631 clock-names = "serial";
1632 resets = <&bpmp TEGRA194_RESET_UARTG>;
1633 reset-names = "serial";
1638 compatible = "nvidia,tegra194-rtc", "nvidia,tegra20-rtc";
1640 interrupt-parent = <&pmc>;
1642 clocks = <&bpmp TEGRA194_CLK_CLK_32K>;
1643 clock-names = "rtc";
1648 compatible = "nvidia,tegra194-gpio-aon";
1649 reg-names = "security", "gpio";
1656 gpio-controller;
1657 #gpio-cells = <2>;
1658 interrupt-controller;
1659 #interrupt-cells = <2>;
1660 gpio-ranges = <&pinmux_aon 0 0 30>;
1664 compatible = "nvidia,tegra194-pinmux-aon";
1671 compatible = "nvidia,tegra194-pwm",
1672 "nvidia,tegra186-pwm";
1674 clocks = <&bpmp TEGRA194_CLK_PWM4>;
1675 resets = <&bpmp TEGRA194_RESET_PWM4>;
1676 reset-names = "pwm";
1678 #pwm-cells = <2>;
1682 compatible = "nvidia,tegra194-pmc";
1688 reg-names = "pmc", "wake", "aotag", "scratch", "misc";
1690 #interrupt-cells = <2>;
1691 interrupt-controller;
1693 sdmmc1_1v8: sdmmc1-1v8 {
1694 pins = "sdmmc1-hv";
1695 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
1698 sdmmc1_3v3: sdmmc1-3v3 {
1699 pins = "sdmmc1-hv";
1700 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
1703 sdmmc3_1v8: sdmmc3-1v8 {
1704 pins = "sdmmc3-hv";
1705 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
1708 sdmmc3_3v3: sdmmc3-3v3 {
1709 pins = "sdmmc3-hv";
1710 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
1714 aon-noc@c600000 {
1715 compatible = "nvidia,tegra194-aon-noc";
1723 bpmp-noc@d600000 {
1724 compatible = "nvidia,tegra194-bpmp-noc";
1734 compatible = "nvidia,tegra194-smmu", "nvidia,smmu-500";
1801 stream-match-mask = <0x7f80>;
1802 #global-interrupts = <1>;
1803 #iommu-cells = <1>;
1805 nvidia,memory-controller = <&mc>;
1810 compatible = "nvidia,tegra194-smmu", "nvidia,smmu-500";
1879 stream-match-mask = <0x7f80>;
1880 #global-interrupts = <2>;
1881 #iommu-cells = <1>;
1883 nvidia,memory-controller = <&mc>;
1888 compatible = "nvidia,tegra194-host1x";
1891 reg-names = "hypervisor", "vm";
1894 interrupt-names = "syncpt", "host1x";
1895 clocks = <&bpmp TEGRA194_CLK_HOST1X>;
1896 clock-names = "host1x";
1897 resets = <&bpmp TEGRA194_RESET_HOST1X>;
1898 reset-names = "host1x";
1900 #address-cells = <2>;
1901 #size-cells = <2>;
1905 interconnect-names = "dma-mem";
1907 dma-coherent;
1910 iommu-map = <0 &smmu TEGRA194_SID_HOST1X_CTX0 1>,
1920 compatible = "nvidia,tegra194-nvdec";
1922 clocks = <&bpmp TEGRA194_CLK_NVDEC1>;
1923 clock-names = "nvdec";
1924 resets = <&bpmp TEGRA194_RESET_NVDEC1>;
1925 reset-names = "nvdec";
1927 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVDECB>;
1931 interconnect-names = "dma-mem", "read-1", "write";
1933 dma-coherent;
1935 nvidia,host1x-class = <0xf5>;
1938 display-hub@15200000 {
1939 compatible = "nvidia,tegra194-display";
1941 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_MISC>,
1942 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP0>,
1943 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP1>,
1944 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP2>,
1945 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP3>,
1946 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP4>,
1947 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP5>;
1948 reset-names = "misc", "wgrp0", "wgrp1", "wgrp2",
1950 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_DISP>,
1951 <&bpmp TEGRA194_CLK_NVDISPLAYHUB>;
1952 clock-names = "disp", "hub";
1955 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1957 #address-cells = <2>;
1958 #size-cells = <2>;
1962 compatible = "nvidia,tegra194-dc";
1965 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P0>;
1966 clock-names = "dc";
1967 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD0>;
1968 reset-names = "dc";
1970 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1973 interconnect-names = "dma-mem", "read-1";
1980 compatible = "nvidia,tegra194-dc";
1983 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P1>;
1984 clock-names = "dc";
1985 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD1>;
1986 reset-names = "dc";
1988 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPB>;
1991 interconnect-names = "dma-mem", "read-1";
1998 compatible = "nvidia,tegra194-dc";
2001 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P2>;
2002 clock-names = "dc";
2003 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD2>;
2004 reset-names = "dc";
2006 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>;
2009 interconnect-names = "dma-mem", "read-1";
2016 compatible = "nvidia,tegra194-dc";
2019 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P3>;
2020 clock-names = "dc";
2021 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD3>;
2022 reset-names = "dc";
2024 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>;
2027 interconnect-names = "dma-mem", "read-1";
2035 compatible = "nvidia,tegra194-vic";
2038 clocks = <&bpmp TEGRA194_CLK_VIC>;
2039 clock-names = "vic";
2040 resets = <&bpmp TEGRA194_RESET_VIC>;
2041 reset-names = "vic";
2043 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_VIC>;
2046 interconnect-names = "dma-mem", "write";
2048 dma-coherent;
2052 compatible = "nvidia,tegra194-nvjpg";
2054 clocks = <&bpmp TEGRA194_CLK_NVJPG>;
2055 clock-names = "nvjpg";
2056 resets = <&bpmp TEGRA194_RESET_NVJPG>;
2057 reset-names = "nvjpg";
2059 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVJPG>;
2062 interconnect-names = "dma-mem", "write";
2064 dma-coherent;
2068 compatible = "nvidia,tegra194-nvdec";
2070 clocks = <&bpmp TEGRA194_CLK_NVDEC>;
2071 clock-names = "nvdec";
2072 resets = <&bpmp TEGRA194_RESET_NVDEC>;
2073 reset-names = "nvdec";
2075 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVDECA>;
2079 interconnect-names = "dma-mem", "read-1", "write";
2081 dma-coherent;
2083 nvidia,host1x-class = <0xf0>;
2087 compatible = "nvidia,tegra194-nvenc";
2089 clocks = <&bpmp TEGRA194_CLK_NVENC>;
2090 clock-names = "nvenc";
2091 resets = <&bpmp TEGRA194_RESET_NVENC>;
2092 reset-names = "nvenc";
2094 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVENCA>;
2098 interconnect-names = "dma-mem", "read-1", "write";
2100 dma-coherent;
2102 nvidia,host1x-class = <0x21>;
2106 compatible = "nvidia,tegra194-dpaux";
2109 clocks = <&bpmp TEGRA194_CLK_DPAUX>,
2110 <&bpmp TEGRA194_CLK_PLLDP>;
2111 clock-names = "dpaux", "parent";
2112 resets = <&bpmp TEGRA194_RESET_DPAUX>;
2113 reset-names = "dpaux";
2116 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
2118 state_dpaux0_aux: pinmux-aux {
2119 groups = "dpaux-io";
2123 state_dpaux0_i2c: pinmux-i2c {
2124 groups = "dpaux-io";
2128 state_dpaux0_off: pinmux-off {
2129 groups = "dpaux-io";
2133 i2c-bus {
2134 #address-cells = <1>;
2135 #size-cells = <0>;
2140 compatible = "nvidia,tegra194-dpaux";
2143 clocks = <&bpmp TEGRA194_CLK_DPAUX1>,
2144 <&bpmp TEGRA194_CLK_PLLDP>;
2145 clock-names = "dpaux", "parent";
2146 resets = <&bpmp TEGRA194_RESET_DPAUX1>;
2147 reset-names = "dpaux";
2150 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
2152 state_dpaux1_aux: pinmux-aux {
2153 groups = "dpaux-io";
2157 state_dpaux1_i2c: pinmux-i2c {
2158 groups = "dpaux-io";
2162 state_dpaux1_off: pinmux-off {
2163 groups = "dpaux-io";
2167 i2c-bus {
2168 #address-cells = <1>;
2169 #size-cells = <0>;
2174 compatible = "nvidia,tegra194-dpaux";
2177 clocks = <&bpmp TEGRA194_CLK_DPAUX2>,
2178 <&bpmp TEGRA194_CLK_PLLDP>;
2179 clock-names = "dpaux", "parent";
2180 resets = <&bpmp TEGRA194_RESET_DPAUX2>;
2181 reset-names = "dpaux";
2184 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
2186 state_dpaux2_aux: pinmux-aux {
2187 groups = "dpaux-io";
2191 state_dpaux2_i2c: pinmux-i2c {
2192 groups = "dpaux-io";
2196 state_dpaux2_off: pinmux-off {
2197 groups = "dpaux-io";
2201 i2c-bus {
2202 #address-cells = <1>;
2203 #size-cells = <0>;
2208 compatible = "nvidia,tegra194-dpaux";
2211 clocks = <&bpmp TEGRA194_CLK_DPAUX3>,
2212 <&bpmp TEGRA194_CLK_PLLDP>;
2213 clock-names = "dpaux", "parent";
2214 resets = <&bpmp TEGRA194_RESET_DPAUX3>;
2215 reset-names = "dpaux";
2218 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
2220 state_dpaux3_aux: pinmux-aux {
2221 groups = "dpaux-io";
2225 state_dpaux3_i2c: pinmux-i2c {
2226 groups = "dpaux-io";
2230 state_dpaux3_off: pinmux-off {
2231 groups = "dpaux-io";
2235 i2c-bus {
2236 #address-cells = <1>;
2237 #size-cells = <0>;
2242 compatible = "nvidia,tegra194-nvenc";
2244 clocks = <&bpmp TEGRA194_CLK_NVENC1>;
2245 clock-names = "nvenc";
2246 resets = <&bpmp TEGRA194_RESET_NVENC1>;
2247 reset-names = "nvenc";
2249 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVENCB>;
2253 interconnect-names = "dma-mem", "read-1", "write";
2255 dma-coherent;
2257 nvidia,host1x-class = <0x22>;
2261 compatible = "nvidia,tegra194-sor";
2264 clocks = <&bpmp TEGRA194_CLK_SOR0_REF>,
2265 <&bpmp TEGRA194_CLK_SOR0_OUT>,
2266 <&bpmp TEGRA194_CLK_PLLD>,
2267 <&bpmp TEGRA194_CLK_PLLDP>,
2268 <&bpmp TEGRA194_CLK_SOR_SAFE>,
2269 <&bpmp TEGRA194_CLK_SOR0_PAD_CLKOUT>;
2270 clock-names = "sor", "out", "parent", "dp", "safe",
2272 resets = <&bpmp TEGRA194_RESET_SOR0>;
2273 reset-names = "sor";
2274 pinctrl-0 = <&state_dpaux0_aux>;
2275 pinctrl-1 = <&state_dpaux0_i2c>;
2276 pinctrl-2 = <&state_dpaux0_off>;
2277 pinctrl-names = "aux", "i2c", "off";
2280 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
2285 compatible = "nvidia,tegra194-sor";
2288 clocks = <&bpmp TEGRA194_CLK_SOR1_REF>,
2289 <&bpmp TEGRA194_CLK_SOR1_OUT>,
2290 <&bpmp TEGRA194_CLK_PLLD2>,
2291 <&bpmp TEGRA194_CLK_PLLDP>,
2292 <&bpmp TEGRA194_CLK_SOR_SAFE>,
2293 <&bpmp TEGRA194_CLK_SOR1_PAD_CLKOUT>;
2294 clock-names = "sor", "out", "parent", "dp", "safe",
2296 resets = <&bpmp TEGRA194_RESET_SOR1>;
2297 reset-names = "sor";
2298 pinctrl-0 = <&state_dpaux1_aux>;
2299 pinctrl-1 = <&state_dpaux1_i2c>;
2300 pinctrl-2 = <&state_dpaux1_off>;
2301 pinctrl-names = "aux", "i2c", "off";
2304 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
2309 compatible = "nvidia,tegra194-sor";
2312 clocks = <&bpmp TEGRA194_CLK_SOR2_REF>,
2313 <&bpmp TEGRA194_CLK_SOR2_OUT>,
2314 <&bpmp TEGRA194_CLK_PLLD3>,
2315 <&bpmp TEGRA194_CLK_PLLDP>,
2316 <&bpmp TEGRA194_CLK_SOR_SAFE>,
2317 <&bpmp TEGRA194_CLK_SOR2_PAD_CLKOUT>;
2318 clock-names = "sor", "out", "parent", "dp", "safe",
2320 resets = <&bpmp TEGRA194_RESET_SOR2>;
2321 reset-names = "sor";
2322 pinctrl-0 = <&state_dpaux2_aux>;
2323 pinctrl-1 = <&state_dpaux2_i2c>;
2324 pinctrl-2 = <&state_dpaux2_off>;
2325 pinctrl-names = "aux", "i2c", "off";
2328 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
2333 compatible = "nvidia,tegra194-sor";
2336 clocks = <&bpmp TEGRA194_CLK_SOR3_REF>,
2337 <&bpmp TEGRA194_CLK_SOR3_OUT>,
2338 <&bpmp TEGRA194_CLK_PLLD4>,
2339 <&bpmp TEGRA194_CLK_PLLDP>,
2340 <&bpmp TEGRA194_CLK_SOR_SAFE>,
2341 <&bpmp TEGRA194_CLK_SOR3_PAD_CLKOUT>;
2342 clock-names = "sor", "out", "parent", "dp", "safe",
2344 resets = <&bpmp TEGRA194_RESET_SOR3>;
2345 reset-names = "sor";
2346 pinctrl-0 = <&state_dpaux3_aux>;
2347 pinctrl-1 = <&state_dpaux3_i2c>;
2348 pinctrl-2 = <&state_dpaux3_off>;
2349 pinctrl-names = "aux", "i2c", "off";
2352 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
2358 compatible = "nvidia,tegra194-pcie";
2359 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>;
2364 reg-names = "appl", "config", "atu_dma", "dbi";
2368 #address-cells = <3>;
2369 #size-cells = <2>;
2371 num-lanes = <1>;
2372 linux,pci-domain = <1>;
2374 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_1>;
2375 clock-names = "core";
2377 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_1_APB>,
2378 <&bpmp TEGRA194_RESET_PEX0_CORE_1>;
2379 reset-names = "apb", "core";
2383 interrupt-names = "intr", "msi";
2385 #interrupt-cells = <1>;
2386 interrupt-map-mask = <0 0 0 0>;
2387 interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
2389 nvidia,bpmp = <&bpmp 1>;
2391 nvidia,aspm-cmrt-us = <60>;
2392 nvidia,aspm-pwr-on-t-us = <20>;
2393 nvidia,aspm-l0s-entrance-latency-us = <3>;
2395 bus-range = <0x0 0xff>;
2398 …00000 0x0 0x40000000 0x12 0x30000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 Ki…
2403 interconnect-names = "dma-mem", "write";
2404 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE1 0x1000>;
2405 iommu-map-mask = <0x0>;
2406 dma-coherent;
2410 compatible = "nvidia,tegra194-pcie";
2411 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>;
2416 reg-names = "appl", "config", "atu_dma", "dbi";
2420 #address-cells = <3>;
2421 #size-cells = <2>;
2423 num-lanes = <1>;
2424 linux,pci-domain = <2>;
2426 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_2>;
2427 clock-names = "core";
2429 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_2_APB>,
2430 <&bpmp TEGRA194_RESET_PEX0_CORE_2>;
2431 reset-names = "apb", "core";
2435 interrupt-names = "intr", "msi";
2437 #interrupt-cells = <1>;
2438 interrupt-map-mask = <0 0 0 0>;
2439 interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
2441 nvidia,bpmp = <&bpmp 2>;
2443 nvidia,aspm-cmrt-us = <60>;
2444 nvidia,aspm-pwr-on-t-us = <20>;
2445 nvidia,aspm-l0s-entrance-latency-us = <3>;
2447 bus-range = <0x0 0xff>;
2450 …00000 0x0 0x40000000 0x12 0x70000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 Ki…
2455 interconnect-names = "dma-mem", "write";
2456 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE2 0x1000>;
2457 iommu-map-mask = <0x0>;
2458 dma-coherent;
2462 compatible = "nvidia,tegra194-pcie";
2463 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>;
2468 reg-names = "appl", "config", "atu_dma", "dbi";
2472 #address-cells = <3>;
2473 #size-cells = <2>;
2475 num-lanes = <1>;
2476 linux,pci-domain = <3>;
2478 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_3>;
2479 clock-names = "core";
2481 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_3_APB>,
2482 <&bpmp TEGRA194_RESET_PEX0_CORE_3>;
2483 reset-names = "apb", "core";
2487 interrupt-names = "intr", "msi";
2489 #interrupt-cells = <1>;
2490 interrupt-map-mask = <0 0 0 0>;
2491 interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
2493 nvidia,bpmp = <&bpmp 3>;
2495 nvidia,aspm-cmrt-us = <60>;
2496 nvidia,aspm-pwr-on-t-us = <20>;
2497 nvidia,aspm-l0s-entrance-latency-us = <3>;
2499 bus-range = <0x0 0xff>;
2502 …<0x02000000 0x0 0x40000000 0x12 0xb0000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB +…
2507 interconnect-names = "dma-mem", "write";
2508 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE3 0x1000>;
2509 iommu-map-mask = <0x0>;
2510 dma-coherent;
2514 compatible = "nvidia,tegra194-pcie";
2515 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>;
2520 reg-names = "appl", "config", "atu_dma", "dbi";
2524 #address-cells = <3>;
2525 #size-cells = <2>;
2527 num-lanes = <4>;
2528 linux,pci-domain = <4>;
2530 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>;
2531 clock-names = "core";
2533 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>,
2534 <&bpmp TEGRA194_RESET_PEX0_CORE_4>;
2535 reset-names = "apb", "core";
2539 interrupt-names = "intr", "msi";
2541 #interrupt-cells = <1>;
2542 interrupt-map-mask = <0 0 0 0>;
2543 interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
2545 nvidia,bpmp = <&bpmp 4>;
2547 nvidia,aspm-cmrt-us = <60>;
2548 nvidia,aspm-pwr-on-t-us = <20>;
2549 nvidia,aspm-l0s-entrance-latency-us = <3>;
2551 bus-range = <0x0 0xff>;
2554 …000000 0x0 0x40000000 0x17 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB…
2559 interconnect-names = "dma-mem", "write";
2560 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE4 0x1000>;
2561 iommu-map-mask = <0x0>;
2562 dma-coherent;
2565 pcie-ep@14160000 {
2566 compatible = "nvidia,tegra194-pcie-ep";
2567 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>;
2572 reg-names = "appl", "atu_dma", "dbi", "addr_space";
2576 num-lanes = <4>;
2577 num-ib-windows = <2>;
2578 num-ob-windows = <8>;
2580 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>;
2581 clock-names = "core";
2583 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>,
2584 <&bpmp TEGRA194_RESET_PEX0_CORE_4>;
2585 reset-names = "apb", "core";
2588 interrupt-names = "intr";
2590 nvidia,bpmp = <&bpmp 4>;
2592 nvidia,aspm-cmrt-us = <60>;
2593 nvidia,aspm-pwr-on-t-us = <20>;
2594 nvidia,aspm-l0s-entrance-latency-us = <3>;
2598 interconnect-names = "dma-mem", "write";
2599 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE4 0x1000>;
2600 iommu-map-mask = <0x0>;
2601 dma-coherent;
2605 compatible = "nvidia,tegra194-pcie";
2606 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>;
2611 reg-names = "appl", "config", "atu_dma", "dbi";
2615 #address-cells = <3>;
2616 #size-cells = <2>;
2618 num-lanes = <8>;
2619 linux,pci-domain = <0>;
2621 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>;
2622 clock-names = "core";
2624 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>,
2625 <&bpmp TEGRA194_RESET_PEX0_CORE_0>;
2626 reset-names = "apb", "core";
2630 interrupt-names = "intr", "msi";
2632 #interrupt-cells = <1>;
2633 interrupt-map-mask = <0 0 0 0>;
2634 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
2636 nvidia,bpmp = <&bpmp 0>;
2638 nvidia,aspm-cmrt-us = <60>;
2639 nvidia,aspm-pwr-on-t-us = <20>;
2640 nvidia,aspm-l0s-entrance-latency-us = <3>;
2642 bus-range = <0x0 0xff>;
2645 …000000 0x0 0x40000000 0x1b 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB…
2650 interconnect-names = "dma-mem", "write";
2651 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE0 0x1000>;
2652 iommu-map-mask = <0x0>;
2653 dma-coherent;
2656 pcie-ep@14180000 {
2657 compatible = "nvidia,tegra194-pcie-ep";
2658 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>;
2663 reg-names = "appl", "atu_dma", "dbi", "addr_space";
2667 num-lanes = <8>;
2668 num-ib-windows = <2>;
2669 num-ob-windows = <8>;
2671 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>;
2672 clock-names = "core";
2674 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>,
2675 <&bpmp TEGRA194_RESET_PEX0_CORE_0>;
2676 reset-names = "apb", "core";
2679 interrupt-names = "intr";
2681 nvidia,bpmp = <&bpmp 0>;
2683 nvidia,aspm-cmrt-us = <60>;
2684 nvidia,aspm-pwr-on-t-us = <20>;
2685 nvidia,aspm-l0s-entrance-latency-us = <3>;
2689 interconnect-names = "dma-mem", "write";
2690 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE0 0x1000>;
2691 iommu-map-mask = <0x0>;
2692 dma-coherent;
2696 compatible = "nvidia,tegra194-pcie";
2697 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>;
2702 reg-names = "appl", "config", "atu_dma", "dbi";
2706 #address-cells = <3>;
2707 #size-cells = <2>;
2709 num-lanes = <8>;
2710 linux,pci-domain = <5>;
2712 pinctrl-names = "default";
2713 pinctrl-0 = <&pex_rst_c5_out_state>, <&pex_clkreq_c5_bi_dir_state>;
2715 clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>;
2716 clock-names = "core";
2718 resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>,
2719 <&bpmp TEGRA194_RESET_PEX1_CORE_5>;
2720 reset-names = "apb", "core";
2724 interrupt-names = "intr", "msi";
2726 nvidia,bpmp = <&bpmp 5>;
2728 #interrupt-cells = <1>;
2729 interrupt-map-mask = <0 0 0 0>;
2730 interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
2732 nvidia,aspm-cmrt-us = <60>;
2733 nvidia,aspm-pwr-on-t-us = <20>;
2734 nvidia,aspm-l0s-entrance-latency-us = <3>;
2736 bus-range = <0x0 0xff>;
2739 …000000 0x0 0x40000000 0x1f 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB…
2744 interconnect-names = "dma-mem", "write";
2745 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE5 0x1000>;
2746 iommu-map-mask = <0x0>;
2747 dma-coherent;
2750 pcie-ep@141a0000 {
2751 compatible = "nvidia,tegra194-pcie-ep";
2752 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>;
2757 reg-names = "appl", "atu_dma", "dbi", "addr_space";
2761 num-lanes = <8>;
2762 num-ib-windows = <2>;
2763 num-ob-windows = <8>;
2765 pinctrl-names = "default";
2766 pinctrl-0 = <&pex_clkreq_c5_bi_dir_state>;
2768 clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>;
2769 clock-names = "core";
2771 resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>,
2772 <&bpmp TEGRA194_RESET_PEX1_CORE_5>;
2773 reset-names = "apb", "core";
2776 interrupt-names = "intr";
2778 nvidia,bpmp = <&bpmp 5>;
2780 nvidia,aspm-cmrt-us = <60>;
2781 nvidia,aspm-pwr-on-t-us = <20>;
2782 nvidia,aspm-l0s-entrance-latency-us = <3>;
2786 interconnect-names = "dma-mem", "write";
2787 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE5 0x1000>;
2788 iommu-map-mask = <0x0>;
2789 dma-coherent;
2798 interrupt-names = "stall", "nonstall";
2799 clocks = <&bpmp TEGRA194_CLK_GPCCLK>,
2800 <&bpmp TEGRA194_CLK_GPU_PWR>,
2801 <&bpmp TEGRA194_CLK_FUSE>;
2802 clock-names = "gpu", "pwr", "fuse";
2803 resets = <&bpmp TEGRA194_RESET_GPU>;
2804 reset-names = "gpu";
2805 dma-coherent;
2807 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_GPU>;
2820 interconnect-names = "dma-mem", "read-0-hp", "write-0",
2821 "read-1", "read-1-hp", "write-1",
2822 "read-2", "read-2-hp", "write-2",
2823 "read-3", "read-3-hp", "write-3";
2828 compatible = "nvidia,tegra194-sysram", "mmio-sram";
2831 #address-cells = <1>;
2832 #size-cells = <1>;
2835 no-memory-wc;
2839 label = "cpu-bpmp-tx";
2845 label = "cpu-bpmp-rx";
2850 bpmp: bpmp { label
2851 compatible = "nvidia,tegra186-bpmp";
2855 #clock-cells = <1>;
2856 #reset-cells = <1>;
2857 #power-domain-cells = <1>;
2862 interconnect-names = "read", "write", "dma-mem", "dma-write";
2866 compatible = "nvidia,tegra186-bpmp-i2c";
2867 nvidia,bpmp-bus-id = <5>;
2868 #address-cells = <1>;
2869 #size-cells = <0>;
2873 compatible = "nvidia,tegra186-bpmp-thermal";
2874 #thermal-sensor-cells = <1>;
2879 compatible = "nvidia,tegra194-ccplex";
2880 nvidia,bpmp = <&bpmp>;
2881 #address-cells = <1>;
2882 #size-cells = <0>;
2884 cpu0_0: cpu@0 {
2885 compatible = "nvidia,tegra194-carmel";
2886 device_type = "cpu";
2888 enable-method = "psci";
2889 i-cache-size = <131072>;
2890 i-cache-line-size = <64>;
2891 i-cache-sets = <512>;
2892 d-cache-size = <65536>;
2893 d-cache-line-size = <64>;
2894 d-cache-sets = <256>;
2895 next-level-cache = <&l2c_0>;
2898 cpu0_1: cpu@1 {
2899 compatible = "nvidia,tegra194-carmel";
2900 device_type = "cpu";
2902 enable-method = "psci";
2903 i-cache-size = <131072>;
2904 i-cache-line-size = <64>;
2905 i-cache-sets = <512>;
2906 d-cache-size = <65536>;
2907 d-cache-line-size = <64>;
2908 d-cache-sets = <256>;
2909 next-level-cache = <&l2c_0>;
2912 cpu1_0: cpu@100 {
2913 compatible = "nvidia,tegra194-carmel";
2914 device_type = "cpu";
2916 enable-method = "psci";
2917 i-cache-size = <131072>;
2918 i-cache-line-size = <64>;
2919 i-cache-sets = <512>;
2920 d-cache-size = <65536>;
2921 d-cache-line-size = <64>;
2922 d-cache-sets = <256>;
2923 next-level-cache = <&l2c_1>;
2926 cpu1_1: cpu@101 {
2927 compatible = "nvidia,tegra194-carmel";
2928 device_type = "cpu";
2930 enable-method = "psci";
2931 i-cache-size = <131072>;
2932 i-cache-line-size = <64>;
2933 i-cache-sets = <512>;
2934 d-cache-size = <65536>;
2935 d-cache-line-size = <64>;
2936 d-cache-sets = <256>;
2937 next-level-cache = <&l2c_1>;
2940 cpu2_0: cpu@200 {
2941 compatible = "nvidia,tegra194-carmel";
2942 device_type = "cpu";
2944 enable-method = "psci";
2945 i-cache-size = <131072>;
2946 i-cache-line-size = <64>;
2947 i-cache-sets = <512>;
2948 d-cache-size = <65536>;
2949 d-cache-line-size = <64>;
2950 d-cache-sets = <256>;
2951 next-level-cache = <&l2c_2>;
2954 cpu2_1: cpu@201 {
2955 compatible = "nvidia,tegra194-carmel";
2956 device_type = "cpu";
2958 enable-method = "psci";
2959 i-cache-size = <131072>;
2960 i-cache-line-size = <64>;
2961 i-cache-sets = <512>;
2962 d-cache-size = <65536>;
2963 d-cache-line-size = <64>;
2964 d-cache-sets = <256>;
2965 next-level-cache = <&l2c_2>;
2968 cpu3_0: cpu@300 {
2969 compatible = "nvidia,tegra194-carmel";
2970 device_type = "cpu";
2972 enable-method = "psci";
2973 i-cache-size = <131072>;
2974 i-cache-line-size = <64>;
2975 i-cache-sets = <512>;
2976 d-cache-size = <65536>;
2977 d-cache-line-size = <64>;
2978 d-cache-sets = <256>;
2979 next-level-cache = <&l2c_3>;
2982 cpu3_1: cpu@301 {
2983 compatible = "nvidia,tegra194-carmel";
2984 device_type = "cpu";
2986 enable-method = "psci";
2987 i-cache-size = <131072>;
2988 i-cache-line-size = <64>;
2989 i-cache-sets = <512>;
2990 d-cache-size = <65536>;
2991 d-cache-line-size = <64>;
2992 d-cache-sets = <256>;
2993 next-level-cache = <&l2c_3>;
2996 cpu-map {
2999 cpu = <&cpu0_0>;
3003 cpu = <&cpu0_1>;
3009 cpu = <&cpu1_0>;
3013 cpu = <&cpu1_1>;
3019 cpu = <&cpu2_0>;
3023 cpu = <&cpu2_1>;
3029 cpu = <&cpu3_0>;
3033 cpu = <&cpu3_1>;
3038 l2c_0: l2-cache0 {
3040 cache-unified;
3041 cache-size = <2097152>;
3042 cache-line-size = <64>;
3043 cache-sets = <2048>;
3044 cache-level = <2>;
3045 next-level-cache = <&l3c>;
3048 l2c_1: l2-cache1 {
3050 cache-unified;
3051 cache-size = <2097152>;
3052 cache-line-size = <64>;
3053 cache-sets = <2048>;
3054 cache-level = <2>;
3055 next-level-cache = <&l3c>;
3058 l2c_2: l2-cache2 {
3060 cache-unified;
3061 cache-size = <2097152>;
3062 cache-line-size = <64>;
3063 cache-sets = <2048>;
3064 cache-level = <2>;
3065 next-level-cache = <&l3c>;
3068 l2c_3: l2-cache3 {
3070 cache-unified;
3071 cache-size = <2097152>;
3072 cache-line-size = <64>;
3073 cache-sets = <2048>;
3074 cache-level = <2>;
3075 next-level-cache = <&l3c>;
3078 l3c: l3-cache {
3080 cache-unified;
3081 cache-size = <4194304>;
3082 cache-line-size = <64>;
3083 cache-level = <3>;
3084 cache-sets = <4096>;
3089 compatible = "nvidia,carmel-pmu";
3098 interrupt-affinity = <&cpu0_0 &cpu0_1 &cpu1_0 &cpu1_1
3103 compatible = "arm,psci-1.0";
3109 compatible = "nvidia,tegra194-tcu";
3112 mbox-names = "rx", "tx";
3118 clocks = <&bpmp TEGRA194_CLK_PLLA>,
3119 <&bpmp TEGRA194_CLK_PLLA_OUT0>;
3120 clock-names = "pll_a", "plla_out0";
3121 assigned-clocks = <&bpmp TEGRA194_CLK_PLLA>,
3122 <&bpmp TEGRA194_CLK_PLLA_OUT0>,
3123 <&bpmp TEGRA194_CLK_AUD_MCLK>;
3124 assigned-clock-parents = <0>,
3125 <&bpmp TEGRA194_CLK_PLLA>,
3126 <&bpmp TEGRA194_CLK_PLLA_OUT0>;
3132 assigned-clock-rates = <258000000>;
3135 thermal-zones {
3136 cpu-thermal {
3137 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_CPU>;
3141 gpu-thermal {
3142 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_GPU>;
3146 aux-thermal {
3147 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_AUX>;
3151 pllx-thermal {
3152 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_PLLX>;
3156 ao-thermal {
3157 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_AO>;
3161 tj-thermal {
3162 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_TJ_MAX>;
3168 compatible = "arm,armv8-timer";
3177 interrupt-parent = <&gic>;
3178 always-on;