Lines Matching full:bpmp
10 #include <dt-bindings/thermal/tegra194-bpmp-thermal.h>
148 clocks = <&bpmp TEGRA194_CLK_AXI_CBB>,
149 <&bpmp TEGRA194_CLK_EQOS_AXI>,
150 <&bpmp TEGRA194_CLK_EQOS_RX>,
151 <&bpmp TEGRA194_CLK_EQOS_TX>,
152 <&bpmp TEGRA194_CLK_EQOS_PTP_REF>;
154 resets = <&bpmp TEGRA194_RESET_EQOS>;
173 resets = <&bpmp TEGRA194_RESET_GPCDMA>;
217 clocks = <&bpmp TEGRA194_CLK_APE>,
218 <&bpmp TEGRA194_CLK_APB2APE>;
220 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_AUD>;
231 clocks = <&bpmp TEGRA194_CLK_AHUB>;
233 assigned-clocks = <&bpmp TEGRA194_CLK_AHUB>;
234 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLP_OUT0>;
246 clocks = <&bpmp TEGRA194_CLK_I2S1>,
247 <&bpmp TEGRA194_CLK_I2S1_SYNC_INPUT>;
249 assigned-clocks = <&bpmp TEGRA194_CLK_I2S1>;
250 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
260 clocks = <&bpmp TEGRA194_CLK_I2S2>,
261 <&bpmp TEGRA194_CLK_I2S2_SYNC_INPUT>;
263 assigned-clocks = <&bpmp TEGRA194_CLK_I2S2>;
264 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
274 clocks = <&bpmp TEGRA194_CLK_I2S3>,
275 <&bpmp TEGRA194_CLK_I2S3_SYNC_INPUT>;
277 assigned-clocks = <&bpmp TEGRA194_CLK_I2S3>;
278 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
288 clocks = <&bpmp TEGRA194_CLK_I2S4>,
289 <&bpmp TEGRA194_CLK_I2S4_SYNC_INPUT>;
291 assigned-clocks = <&bpmp TEGRA194_CLK_I2S4>;
292 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
302 clocks = <&bpmp TEGRA194_CLK_I2S5>,
303 <&bpmp TEGRA194_CLK_I2S5_SYNC_INPUT>;
305 assigned-clocks = <&bpmp TEGRA194_CLK_I2S5>;
306 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
316 clocks = <&bpmp TEGRA194_CLK_I2S6>,
317 <&bpmp TEGRA194_CLK_I2S6_SYNC_INPUT>;
319 assigned-clocks = <&bpmp TEGRA194_CLK_I2S6>;
320 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
422 clocks = <&bpmp TEGRA194_CLK_DMIC1>;
424 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC1>;
425 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
435 clocks = <&bpmp TEGRA194_CLK_DMIC2>;
437 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC2>;
438 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
448 clocks = <&bpmp TEGRA194_CLK_DMIC3>;
450 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC3>;
451 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
461 clocks = <&bpmp TEGRA194_CLK_DMIC4>;
463 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC4>;
464 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
474 clocks = <&bpmp TEGRA194_CLK_DSPK1>;
476 assigned-clocks = <&bpmp TEGRA194_CLK_DSPK1>;
477 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
487 clocks = <&bpmp TEGRA194_CLK_DSPK2>;
489 assigned-clocks = <&bpmp TEGRA194_CLK_DSPK2>;
490 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
642 clocks = <&bpmp TEGRA194_CLK_AHUB>;
657 clocks = <&bpmp TEGRA194_CLK_APE>;
718 clocks = <&bpmp TEGRA194_CLK_EMC>;
723 nvidia,bpmp = <&bpmp>;
748 clocks = <&bpmp TEGRA194_CLK_UARTA>;
749 resets = <&bpmp TEGRA194_RESET_UARTA>;
758 clocks = <&bpmp TEGRA194_CLK_UARTB>;
759 resets = <&bpmp TEGRA194_RESET_UARTB>;
768 clocks = <&bpmp TEGRA194_CLK_UARTD>;
770 resets = <&bpmp TEGRA194_RESET_UARTD>;
780 clocks = <&bpmp TEGRA194_CLK_UARTE>;
782 resets = <&bpmp TEGRA194_RESET_UARTE>;
792 clocks = <&bpmp TEGRA194_CLK_UARTF>;
794 resets = <&bpmp TEGRA194_RESET_UARTF>;
805 clocks = <&bpmp TEGRA194_CLK_I2C1>;
807 resets = <&bpmp TEGRA194_RESET_I2C1>;
819 clocks = <&bpmp TEGRA194_CLK_UARTH>;
821 resets = <&bpmp TEGRA194_RESET_UARTH>;
832 clocks = <&bpmp TEGRA194_CLK_I2C3>;
834 resets = <&bpmp TEGRA194_RESET_I2C3>;
848 clocks = <&bpmp TEGRA194_CLK_I2C4>;
850 resets = <&bpmp TEGRA194_RESET_I2C4>;
867 clocks = <&bpmp TEGRA194_CLK_I2C6>;
869 resets = <&bpmp TEGRA194_RESET_I2C6>;
886 clocks = <&bpmp TEGRA194_CLK_I2C7>;
888 resets = <&bpmp TEGRA194_RESET_I2C7>;
905 clocks = <&bpmp TEGRA194_CLK_I2C9>;
907 resets = <&bpmp TEGRA194_RESET_I2C9>;
923 clocks = <&bpmp TEGRA194_CLK_QSPI0>,
924 <&bpmp TEGRA194_CLK_QSPI0_PM>;
926 resets = <&bpmp TEGRA194_RESET_QSPI0>;
934 clocks = <&bpmp TEGRA194_CLK_PWM1>;
935 resets = <&bpmp TEGRA194_RESET_PWM1>;
945 clocks = <&bpmp TEGRA194_CLK_PWM2>;
946 resets = <&bpmp TEGRA194_RESET_PWM2>;
956 clocks = <&bpmp TEGRA194_CLK_PWM3>;
957 resets = <&bpmp TEGRA194_RESET_PWM3>;
967 clocks = <&bpmp TEGRA194_CLK_PWM5>;
968 resets = <&bpmp TEGRA194_RESET_PWM5>;
978 clocks = <&bpmp TEGRA194_CLK_PWM6>;
979 resets = <&bpmp TEGRA194_RESET_PWM6>;
989 clocks = <&bpmp TEGRA194_CLK_PWM7>;
990 resets = <&bpmp TEGRA194_RESET_PWM7>;
1000 clocks = <&bpmp TEGRA194_CLK_PWM8>;
1001 resets = <&bpmp TEGRA194_RESET_PWM8>;
1013 clocks = <&bpmp TEGRA194_CLK_QSPI1>,
1014 <&bpmp TEGRA194_CLK_QSPI1_PM>;
1016 resets = <&bpmp TEGRA194_RESET_QSPI1>;
1024 clocks = <&bpmp TEGRA194_CLK_SDMMC1>,
1025 <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>;
1027 assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC1>,
1028 <&bpmp TEGRA194_CLK_PLLC4_MUXED>;
1030 <&bpmp TEGRA194_CLK_PLLC4_MUXED>,
1031 <&bpmp TEGRA194_CLK_PLLC4_VCO_DIV2>;
1032 resets = <&bpmp TEGRA194_RESET_SDMMC1>;
1063 clocks = <&bpmp TEGRA194_CLK_SDMMC3>,
1064 <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>;
1066 assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC3>,
1067 <&bpmp TEGRA194_CLK_PLLC4_MUXED>;
1069 <&bpmp TEGRA194_CLK_PLLC4_MUXED>,
1070 <&bpmp TEGRA194_CLK_PLLC4_VCO_DIV2>;
1071 resets = <&bpmp TEGRA194_RESET_SDMMC3>;
1103 clocks = <&bpmp TEGRA194_CLK_SDMMC4>,
1104 <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>;
1106 assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC4>,
1107 <&bpmp TEGRA194_CLK_PLLC4>;
1109 <&bpmp TEGRA194_CLK_PLLC4>;
1110 resets = <&bpmp TEGRA194_RESET_SDMMC4>;
1140 clocks = <&bpmp TEGRA194_CLK_HDA>,
1141 <&bpmp TEGRA194_CLK_HDA2HDMICODEC>,
1142 <&bpmp TEGRA194_CLK_HDA2CODEC_2X>;
1144 resets = <&bpmp TEGRA194_RESET_HDA>,
1145 <&bpmp TEGRA194_RESET_HDA2HDMICODEC>;
1147 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1162 resets = <&bpmp TEGRA194_RESET_XUSB_PADCTL>;
1169 clocks = <&bpmp TEGRA194_CLK_USB2_TRK>;
1269 clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_DEV>,
1270 <&bpmp TEGRA194_CLK_XUSB_CORE_SS>,
1271 <&bpmp TEGRA194_CLK_XUSB_SS>,
1272 <&bpmp TEGRA194_CLK_XUSB_FS>;
1278 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBB>,
1279 <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>;
1295 clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_HOST>,
1296 <&bpmp TEGRA194_CLK_XUSB_FALCON>,
1297 <&bpmp TEGRA194_CLK_XUSB_CORE_SS>,
1298 <&bpmp TEGRA194_CLK_XUSB_SS>,
1299 <&bpmp TEGRA194_CLK_CLK_M>,
1300 <&bpmp TEGRA194_CLK_XUSB_FS>,
1301 <&bpmp TEGRA194_CLK_UTMIPLL>,
1302 <&bpmp TEGRA194_CLK_CLK_M>,
1303 <&bpmp TEGRA194_CLK_PLLE>;
1313 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBC>,
1314 <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>;
1324 clocks = <&bpmp TEGRA194_CLK_FUSE>;
1345 clocks = <&bpmp TEGRA194_CLK_CEC>;
1589 clocks = <&bpmp TEGRA194_CLK_I2C2>;
1591 resets = <&bpmp TEGRA194_RESET_I2C2>;
1604 clocks = <&bpmp TEGRA194_CLK_I2C8>;
1606 resets = <&bpmp TEGRA194_RESET_I2C8>;
1618 clocks = <&bpmp TEGRA194_CLK_UARTC>;
1620 resets = <&bpmp TEGRA194_RESET_UARTC>;
1630 clocks = <&bpmp TEGRA194_CLK_UARTG>;
1632 resets = <&bpmp TEGRA194_RESET_UARTG>;
1642 clocks = <&bpmp TEGRA194_CLK_CLK_32K>;
1674 clocks = <&bpmp TEGRA194_CLK_PWM4>;
1675 resets = <&bpmp TEGRA194_RESET_PWM4>;
1723 bpmp-noc@d600000 {
1724 compatible = "nvidia,tegra194-bpmp-noc";
1895 clocks = <&bpmp TEGRA194_CLK_HOST1X>;
1897 resets = <&bpmp TEGRA194_RESET_HOST1X>;
1922 clocks = <&bpmp TEGRA194_CLK_NVDEC1>;
1924 resets = <&bpmp TEGRA194_RESET_NVDEC1>;
1927 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVDECB>;
1941 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_MISC>,
1942 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP0>,
1943 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP1>,
1944 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP2>,
1945 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP3>,
1946 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP4>,
1947 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP5>;
1950 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_DISP>,
1951 <&bpmp TEGRA194_CLK_NVDISPLAYHUB>;
1955 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1965 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P0>;
1967 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD0>;
1970 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1983 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P1>;
1985 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD1>;
1988 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPB>;
2001 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P2>;
2003 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD2>;
2006 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>;
2019 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P3>;
2021 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD3>;
2024 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>;
2038 clocks = <&bpmp TEGRA194_CLK_VIC>;
2040 resets = <&bpmp TEGRA194_RESET_VIC>;
2043 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_VIC>;
2054 clocks = <&bpmp TEGRA194_CLK_NVJPG>;
2056 resets = <&bpmp TEGRA194_RESET_NVJPG>;
2059 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVJPG>;
2070 clocks = <&bpmp TEGRA194_CLK_NVDEC>;
2072 resets = <&bpmp TEGRA194_RESET_NVDEC>;
2075 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVDECA>;
2089 clocks = <&bpmp TEGRA194_CLK_NVENC>;
2091 resets = <&bpmp TEGRA194_RESET_NVENC>;
2094 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVENCA>;
2109 clocks = <&bpmp TEGRA194_CLK_DPAUX>,
2110 <&bpmp TEGRA194_CLK_PLLDP>;
2112 resets = <&bpmp TEGRA194_RESET_DPAUX>;
2116 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
2143 clocks = <&bpmp TEGRA194_CLK_DPAUX1>,
2144 <&bpmp TEGRA194_CLK_PLLDP>;
2146 resets = <&bpmp TEGRA194_RESET_DPAUX1>;
2150 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
2177 clocks = <&bpmp TEGRA194_CLK_DPAUX2>,
2178 <&bpmp TEGRA194_CLK_PLLDP>;
2180 resets = <&bpmp TEGRA194_RESET_DPAUX2>;
2184 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
2211 clocks = <&bpmp TEGRA194_CLK_DPAUX3>,
2212 <&bpmp TEGRA194_CLK_PLLDP>;
2214 resets = <&bpmp TEGRA194_RESET_DPAUX3>;
2218 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
2244 clocks = <&bpmp TEGRA194_CLK_NVENC1>;
2246 resets = <&bpmp TEGRA194_RESET_NVENC1>;
2249 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVENCB>;
2264 clocks = <&bpmp TEGRA194_CLK_SOR0_REF>,
2265 <&bpmp TEGRA194_CLK_SOR0_OUT>,
2266 <&bpmp TEGRA194_CLK_PLLD>,
2267 <&bpmp TEGRA194_CLK_PLLDP>,
2268 <&bpmp TEGRA194_CLK_SOR_SAFE>,
2269 <&bpmp TEGRA194_CLK_SOR0_PAD_CLKOUT>;
2272 resets = <&bpmp TEGRA194_RESET_SOR0>;
2280 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
2288 clocks = <&bpmp TEGRA194_CLK_SOR1_REF>,
2289 <&bpmp TEGRA194_CLK_SOR1_OUT>,
2290 <&bpmp TEGRA194_CLK_PLLD2>,
2291 <&bpmp TEGRA194_CLK_PLLDP>,
2292 <&bpmp TEGRA194_CLK_SOR_SAFE>,
2293 <&bpmp TEGRA194_CLK_SOR1_PAD_CLKOUT>;
2296 resets = <&bpmp TEGRA194_RESET_SOR1>;
2304 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
2312 clocks = <&bpmp TEGRA194_CLK_SOR2_REF>,
2313 <&bpmp TEGRA194_CLK_SOR2_OUT>,
2314 <&bpmp TEGRA194_CLK_PLLD3>,
2315 <&bpmp TEGRA194_CLK_PLLDP>,
2316 <&bpmp TEGRA194_CLK_SOR_SAFE>,
2317 <&bpmp TEGRA194_CLK_SOR2_PAD_CLKOUT>;
2320 resets = <&bpmp TEGRA194_RESET_SOR2>;
2328 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
2336 clocks = <&bpmp TEGRA194_CLK_SOR3_REF>,
2337 <&bpmp TEGRA194_CLK_SOR3_OUT>,
2338 <&bpmp TEGRA194_CLK_PLLD4>,
2339 <&bpmp TEGRA194_CLK_PLLDP>,
2340 <&bpmp TEGRA194_CLK_SOR_SAFE>,
2341 <&bpmp TEGRA194_CLK_SOR3_PAD_CLKOUT>;
2344 resets = <&bpmp TEGRA194_RESET_SOR3>;
2352 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
2359 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>;
2374 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_1>;
2377 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_1_APB>,
2378 <&bpmp TEGRA194_RESET_PEX0_CORE_1>;
2389 nvidia,bpmp = <&bpmp 1>;
2411 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>;
2426 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_2>;
2429 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_2_APB>,
2430 <&bpmp TEGRA194_RESET_PEX0_CORE_2>;
2441 nvidia,bpmp = <&bpmp 2>;
2463 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>;
2478 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_3>;
2481 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_3_APB>,
2482 <&bpmp TEGRA194_RESET_PEX0_CORE_3>;
2493 nvidia,bpmp = <&bpmp 3>;
2515 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>;
2530 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>;
2533 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>,
2534 <&bpmp TEGRA194_RESET_PEX0_CORE_4>;
2545 nvidia,bpmp = <&bpmp 4>;
2567 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>;
2580 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>;
2583 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>,
2584 <&bpmp TEGRA194_RESET_PEX0_CORE_4>;
2590 nvidia,bpmp = <&bpmp 4>;
2606 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>;
2621 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>;
2624 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>,
2625 <&bpmp TEGRA194_RESET_PEX0_CORE_0>;
2636 nvidia,bpmp = <&bpmp 0>;
2658 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>;
2671 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>;
2674 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>,
2675 <&bpmp TEGRA194_RESET_PEX0_CORE_0>;
2681 nvidia,bpmp = <&bpmp 0>;
2697 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>;
2715 clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>;
2718 resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>,
2719 <&bpmp TEGRA194_RESET_PEX1_CORE_5>;
2726 nvidia,bpmp = <&bpmp 5>;
2752 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>;
2768 clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>;
2771 resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>,
2772 <&bpmp TEGRA194_RESET_PEX1_CORE_5>;
2778 nvidia,bpmp = <&bpmp 5>;
2799 clocks = <&bpmp TEGRA194_CLK_GPCCLK>,
2800 <&bpmp TEGRA194_CLK_GPU_PWR>,
2801 <&bpmp TEGRA194_CLK_FUSE>;
2803 resets = <&bpmp TEGRA194_RESET_GPU>;
2807 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_GPU>;
2839 label = "cpu-bpmp-tx";
2845 label = "cpu-bpmp-rx";
2850 bpmp: bpmp { label
2851 compatible = "nvidia,tegra186-bpmp";
2866 compatible = "nvidia,tegra186-bpmp-i2c";
2867 nvidia,bpmp-bus-id = <5>;
2873 compatible = "nvidia,tegra186-bpmp-thermal";
2880 nvidia,bpmp = <&bpmp>;
3118 clocks = <&bpmp TEGRA194_CLK_PLLA>,
3119 <&bpmp TEGRA194_CLK_PLLA_OUT0>;
3121 assigned-clocks = <&bpmp TEGRA194_CLK_PLLA>,
3122 <&bpmp TEGRA194_CLK_PLLA_OUT0>,
3123 <&bpmp TEGRA194_CLK_AUD_MCLK>;
3125 <&bpmp TEGRA194_CLK_PLLA>,
3126 <&bpmp TEGRA194_CLK_PLLA_OUT0>;
3137 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_CPU>;
3142 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_GPU>;
3147 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_AUX>;
3152 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_PLLX>;
3157 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_AO>;
3162 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_TJ_MAX>;