Lines Matching full:bpmp

10 #include <dt-bindings/thermal/tegra186-bpmp-thermal.h>
55 		clocks = <&bpmp TEGRA186_CLK_AXI_CBB>,
56 			 <&bpmp TEGRA186_CLK_EQOS_AXI>,
57 			 <&bpmp TEGRA186_CLK_EQOS_RX>,
58 			 <&bpmp TEGRA186_CLK_EQOS_TX>,
59 			 <&bpmp TEGRA186_CLK_EQOS_PTP_REF>;
61 		resets = <&bpmp TEGRA186_RESET_EQOS>;
79 		resets = <&bpmp TEGRA186_RESET_GPCDMA>;
123 		clocks = <&bpmp TEGRA186_CLK_APE>,
124 			 <&bpmp TEGRA186_CLK_APB2APE>;
126 		power-domains = <&bpmp TEGRA186_POWER_DOMAIN_AUD>;
135 			clocks = <&bpmp TEGRA186_CLK_AHUB>;
137 			assigned-clocks = <&bpmp TEGRA186_CLK_AHUB>;
138 			assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>;
149 				clocks = <&bpmp TEGRA186_CLK_I2S1>,
150 					 <&bpmp TEGRA186_CLK_I2S1_SYNC_INPUT>;
152 				assigned-clocks = <&bpmp TEGRA186_CLK_I2S1>;
153 				assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
163 				clocks = <&bpmp TEGRA186_CLK_I2S2>,
164 					 <&bpmp TEGRA186_CLK_I2S2_SYNC_INPUT>;
166 				assigned-clocks = <&bpmp TEGRA186_CLK_I2S2>;
167 				assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
177 				clocks = <&bpmp TEGRA186_CLK_I2S3>,
178 					 <&bpmp TEGRA186_CLK_I2S3_SYNC_INPUT>;
180 				assigned-clocks = <&bpmp TEGRA186_CLK_I2S3>;
181 				assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
191 				clocks = <&bpmp TEGRA186_CLK_I2S4>,
192 					 <&bpmp TEGRA186_CLK_I2S4_SYNC_INPUT>;
194 				assigned-clocks = <&bpmp TEGRA186_CLK_I2S4>;
195 				assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
205 				clocks = <&bpmp TEGRA186_CLK_I2S5>,
206 					 <&bpmp TEGRA186_CLK_I2S5_SYNC_INPUT>;
208 				assigned-clocks = <&bpmp TEGRA186_CLK_I2S5>;
209 				assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
219 				clocks = <&bpmp TEGRA186_CLK_I2S6>,
220 					 <&bpmp TEGRA186_CLK_I2S6_SYNC_INPUT>;
222 				assigned-clocks = <&bpmp TEGRA186_CLK_I2S6>;
223 				assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
328 				clocks = <&bpmp TEGRA186_CLK_DMIC1>;
330 				assigned-clocks = <&bpmp TEGRA186_CLK_DMIC1>;
331 				assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
340 				clocks = <&bpmp TEGRA186_CLK_DMIC2>;
342 				assigned-clocks = <&bpmp TEGRA186_CLK_DMIC2>;
343 				assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
352 				clocks = <&bpmp TEGRA186_CLK_DMIC3>;
354 				assigned-clocks = <&bpmp TEGRA186_CLK_DMIC3>;
355 				assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
364 				clocks = <&bpmp TEGRA186_CLK_DMIC4>;
366 				assigned-clocks = <&bpmp TEGRA186_CLK_DMIC4>;
367 				assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
376 				clocks = <&bpmp TEGRA186_CLK_DSPK1>;
378 				assigned-clocks = <&bpmp TEGRA186_CLK_DSPK1>;
379 				assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
388 				clocks = <&bpmp TEGRA186_CLK_DSPK2>;
390 				assigned-clocks = <&bpmp TEGRA186_CLK_DSPK2>;
391 				assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
535 			clocks = <&bpmp TEGRA186_CLK_AHUB>;
549 			clocks = <&bpmp TEGRA186_CLK_APE>;
583 			clocks = <&bpmp TEGRA186_CLK_EMC>;
588 			nvidia,bpmp = <&bpmp>;
613 		clocks = <&bpmp TEGRA186_CLK_UARTA>;
614 		resets = <&bpmp TEGRA186_RESET_UARTA>;
623 		clocks = <&bpmp TEGRA186_CLK_UARTB>;
625 		resets = <&bpmp TEGRA186_RESET_UARTB>;
635 		clocks = <&bpmp TEGRA186_CLK_UARTD>;
637 		resets = <&bpmp TEGRA186_RESET_UARTD>;
647 		clocks = <&bpmp TEGRA186_CLK_UARTE>;
649 		resets = <&bpmp TEGRA186_RESET_UARTE>;
659 		clocks = <&bpmp TEGRA186_CLK_UARTF>;
661 		resets = <&bpmp TEGRA186_RESET_UARTF>;
672 		clocks = <&bpmp TEGRA186_CLK_I2C1>;
674 		resets = <&bpmp TEGRA186_RESET_I2C1>;
687 		clocks = <&bpmp TEGRA186_CLK_I2C3>;
689 		resets = <&bpmp TEGRA186_RESET_I2C3>;
703 		clocks = <&bpmp TEGRA186_CLK_I2C4>;
705 		resets = <&bpmp TEGRA186_RESET_I2C4>;
715 	/* controlled by BPMP, should not be enabled */
722 		clocks = <&bpmp TEGRA186_CLK_I2C5>;
724 		resets = <&bpmp TEGRA186_RESET_I2C5>;
736 		clocks = <&bpmp TEGRA186_CLK_I2C6>;
738 		resets = <&bpmp TEGRA186_RESET_I2C6>;
754 		clocks = <&bpmp TEGRA186_CLK_I2C7>;
756 		resets = <&bpmp TEGRA186_RESET_I2C7>;
769 		clocks = <&bpmp TEGRA186_CLK_I2C9>;
771 		resets = <&bpmp TEGRA186_RESET_I2C9>;
781 		clocks = <&bpmp TEGRA186_CLK_PWM1>;
782 		resets = <&bpmp TEGRA186_RESET_PWM1>;
791 		clocks = <&bpmp TEGRA186_CLK_PWM2>;
792 		resets = <&bpmp TEGRA186_RESET_PWM2>;
801 		clocks = <&bpmp TEGRA186_CLK_PWM3>;
802 		resets = <&bpmp TEGRA186_RESET_PWM3>;
811 		clocks = <&bpmp TEGRA186_CLK_PWM5>;
812 		resets = <&bpmp TEGRA186_RESET_PWM5>;
821 		clocks = <&bpmp TEGRA186_CLK_PWM6>;
822 		resets = <&bpmp TEGRA186_RESET_PWM6>;
831 		clocks = <&bpmp TEGRA186_CLK_PWM7>;
832 		resets = <&bpmp TEGRA186_RESET_PWM7>;
841 		clocks = <&bpmp TEGRA186_CLK_PWM8>;
842 		resets = <&bpmp TEGRA186_RESET_PWM8>;
852 		clocks = <&bpmp TEGRA186_CLK_SDMMC1>,
853 			 <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>;
855 		resets = <&bpmp TEGRA186_RESET_SDMMC1>;
872 		assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC1>,
873 				  <&bpmp TEGRA186_CLK_PLLP_OUT0>;
874 		assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>;
882 		clocks = <&bpmp TEGRA186_CLK_SDMMC2>,
883 			 <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>;
885 		resets = <&bpmp TEGRA186_RESET_SDMMC2>;
907 		clocks = <&bpmp TEGRA186_CLK_SDMMC3>,
908 			 <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>;
910 		resets = <&bpmp TEGRA186_RESET_SDMMC3>;
934 		clocks = <&bpmp TEGRA186_CLK_SDMMC4>,
935 			 <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>;
937 		assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC4>,
938 				  <&bpmp TEGRA186_CLK_PLLC4_VCO>;
939 		assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLC4_VCO>;
940 		resets = <&bpmp TEGRA186_RESET_SDMMC4>;
967 		power-domains = <&bpmp TEGRA186_POWER_DOMAIN_SAX>;
973 		clocks = <&bpmp TEGRA186_CLK_SATA>,
974 			 <&bpmp TEGRA186_CLK_SATA_OOB>;
976 		assigned-clocks = <&bpmp TEGRA186_CLK_SATA>,
977 				  <&bpmp TEGRA186_CLK_SATA_OOB>;
978 		assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>,
979 					 <&bpmp TEGRA186_CLK_PLLP>;
982 		resets = <&bpmp TEGRA186_RESET_SATA>,
983 			<&bpmp TEGRA186_RESET_SATACOLD>;
992 		clocks = <&bpmp TEGRA186_CLK_HDA>,
993 			 <&bpmp TEGRA186_CLK_HDA2HDMICODEC>,
994 			 <&bpmp TEGRA186_CLK_HDA2CODEC_2X>;
996 		resets = <&bpmp TEGRA186_RESET_HDA>,
997 			 <&bpmp TEGRA186_RESET_HDA2HDMICODEC>,
998 			 <&bpmp TEGRA186_RESET_HDA2CODEC_2X>;
1000 		power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1015 		resets = <&bpmp TEGRA186_RESET_XUSB_PADCTL>;
1022 				clocks = <&bpmp TEGRA186_CLK_USB2_TRK>;
1045 				clocks = <&bpmp TEGRA186_CLK_HSIC_TRK>;
1117 		clocks = <&bpmp TEGRA186_CLK_XUSB_HOST>,
1118 			 <&bpmp TEGRA186_CLK_XUSB_FALCON>,
1119 			 <&bpmp TEGRA186_CLK_XUSB_SS>,
1120 			 <&bpmp TEGRA186_CLK_XUSB_CORE_SS>,
1121 			 <&bpmp TEGRA186_CLK_CLK_M>,
1122 			 <&bpmp TEGRA186_CLK_XUSB_FS>,
1123 			 <&bpmp TEGRA186_CLK_PLLU>,
1124 			 <&bpmp TEGRA186_CLK_CLK_M>,
1125 			 <&bpmp TEGRA186_CLK_PLLE>;
1129 		power-domains = <&bpmp TEGRA186_POWER_DOMAIN_XUSBC>,
1130 				<&bpmp TEGRA186_POWER_DOMAIN_XUSBA>;
1149 		clocks = <&bpmp TEGRA186_CLK_XUSB_CORE_DEV>,
1150 			 <&bpmp TEGRA186_CLK_XUSB_SS>,
1151 			 <&bpmp TEGRA186_CLK_XUSB_CORE_SS>,
1152 			 <&bpmp TEGRA186_CLK_XUSB_FS>;
1158 		power-domains = <&bpmp TEGRA186_POWER_DOMAIN_XUSBB>,
1159 				<&bpmp TEGRA186_POWER_DOMAIN_XUSBA>;
1168 		clocks = <&bpmp TEGRA186_CLK_FUSE>;
1189 		clocks = <&bpmp TEGRA186_CLK_CEC>;
1209 		clocks = <&bpmp TEGRA186_CLK_I2C2>;
1211 		resets = <&bpmp TEGRA186_RESET_I2C2>;
1224 		clocks = <&bpmp TEGRA186_CLK_I2C8>;
1226 		resets = <&bpmp TEGRA186_RESET_I2C8>;
1238 		clocks = <&bpmp TEGRA186_CLK_UARTC>;
1240 		resets = <&bpmp TEGRA186_RESET_UARTC>;
1250 		clocks = <&bpmp TEGRA186_CLK_UARTG>;
1252 		resets = <&bpmp TEGRA186_RESET_UARTG>;
1262 		clocks = <&bpmp TEGRA186_CLK_CLK_32K>;
1282 		clocks = <&bpmp TEGRA186_CLK_PWM4>;
1283 		resets = <&bpmp TEGRA186_RESET_PWM4>;
1335 		nvidia,bpmp = <&bpmp>;
1340 		power-domains = <&bpmp TEGRA186_POWER_DOMAIN_PCX>;
1366 		clocks = <&bpmp TEGRA186_CLK_PCIE>,
1367 			 <&bpmp TEGRA186_CLK_AFI>,
1368 			 <&bpmp TEGRA186_CLK_PLLE>;
1371 		resets = <&bpmp TEGRA186_RESET_PCIE>,
1372 			 <&bpmp TEGRA186_RESET_AFI>,
1373 			 <&bpmp TEGRA186_RESET_PCIEXCLK>;
1509 		clocks = <&bpmp TEGRA186_CLK_HOST1X>;
1511 		resets = <&bpmp TEGRA186_RESET_HOST1X>;
1538 			clocks = <&bpmp TEGRA186_CLK_DPAUX1>,
1539 				 <&bpmp TEGRA186_CLK_PLLDP>;
1541 			resets = <&bpmp TEGRA186_RESET_DPAUX1>;
1545 			power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1571 			resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_MISC>,
1572 				 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP0>,
1573 				 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP1>,
1574 				 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP2>,
1575 				 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP3>,
1576 				 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP4>,
1577 				 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP5>;
1580 			clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_DISP>,
1581 				 <&bpmp TEGRA186_CLK_NVDISPLAY_DSC>,
1582 				 <&bpmp TEGRA186_CLK_NVDISPLAYHUB>;
1586 			power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1597 				clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P0>;
1599 				resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD0>;
1602 				power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1616 				clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P1>;
1618 				resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD1>;
1621 				power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPB>;
1635 				clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P2>;
1637 				resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD2>;
1640 				power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPC>;
1655 			clocks = <&bpmp TEGRA186_CLK_DSI>,
1656 				 <&bpmp TEGRA186_CLK_DSIA_LP>,
1657 				 <&bpmp TEGRA186_CLK_PLLD>;
1659 			resets = <&bpmp TEGRA186_RESET_DSI>;
1663 			power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1670 			clocks = <&bpmp TEGRA186_CLK_VIC>;
1672 			resets = <&bpmp TEGRA186_RESET_VIC>;
1675 			power-domains = <&bpmp TEGRA186_POWER_DOMAIN_VIC>;
1685 			clocks = <&bpmp TEGRA186_CLK_NVJPG>;
1687 			resets = <&bpmp TEGRA186_RESET_NVJPG>;
1690 			power-domains = <&bpmp TEGRA186_POWER_DOMAIN_NVJPG>;
1701 			clocks = <&bpmp TEGRA186_CLK_DSIB>,
1702 				 <&bpmp TEGRA186_CLK_DSIB_LP>,
1703 				 <&bpmp TEGRA186_CLK_PLLD>;
1705 			resets = <&bpmp TEGRA186_RESET_DSIB>;
1709 			power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1715 			clocks = <&bpmp TEGRA186_CLK_NVDEC>;
1717 			resets = <&bpmp TEGRA186_RESET_NVDEC>;
1720 			power-domains = <&bpmp TEGRA186_POWER_DOMAIN_NVDEC>;
1731 			clocks = <&bpmp TEGRA186_CLK_NVENC>;
1733 			resets = <&bpmp TEGRA186_RESET_NVENC>;
1736 			power-domains = <&bpmp TEGRA186_POWER_DOMAIN_MPE>;
1747 			clocks = <&bpmp TEGRA186_CLK_SOR0>,
1748 				 <&bpmp TEGRA186_CLK_SOR0_OUT>,
1749 				 <&bpmp TEGRA186_CLK_PLLD2>,
1750 				 <&bpmp TEGRA186_CLK_PLLDP>,
1751 				 <&bpmp TEGRA186_CLK_SOR_SAFE>,
1752 				 <&bpmp TEGRA186_CLK_SOR0_PAD_CLKOUT>;
1755 			resets = <&bpmp TEGRA186_RESET_SOR0>;
1763 			power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1771 			clocks = <&bpmp TEGRA186_CLK_SOR1>,
1772 				 <&bpmp TEGRA186_CLK_SOR1_OUT>,
1773 				 <&bpmp TEGRA186_CLK_PLLD3>,
1774 				 <&bpmp TEGRA186_CLK_PLLDP>,
1775 				 <&bpmp TEGRA186_CLK_SOR_SAFE>,
1776 				 <&bpmp TEGRA186_CLK_SOR1_PAD_CLKOUT>;
1779 			resets = <&bpmp TEGRA186_RESET_SOR1>;
1787 			power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1795 			clocks = <&bpmp TEGRA186_CLK_DPAUX>,
1796 				 <&bpmp TEGRA186_CLK_PLLDP>;
1798 			resets = <&bpmp TEGRA186_RESET_DPAUX>;
1802 			power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1828 			resets = <&bpmp TEGRA186_RESET_DSI>;
1837 			clocks = <&bpmp TEGRA186_CLK_DSIC>,
1838 				 <&bpmp TEGRA186_CLK_DSIC_LP>,
1839 				 <&bpmp TEGRA186_CLK_PLLD>;
1841 			resets = <&bpmp TEGRA186_RESET_DSIC>;
1845 			power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1852 			clocks = <&bpmp TEGRA186_CLK_DSID>,
1853 				 <&bpmp TEGRA186_CLK_DSID_LP>,
1854 				 <&bpmp TEGRA186_CLK_PLLD>;
1856 			resets = <&bpmp TEGRA186_RESET_DSID>;
1860 			power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1872 		clocks = <&bpmp TEGRA186_CLK_GPCCLK>,
1873 			 <&bpmp TEGRA186_CLK_GPU>;
1875 		resets = <&bpmp TEGRA186_RESET_GPU>;
1879 		power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>;
1897 			label = "cpu-bpmp-tx";
1903 			label = "cpu-bpmp-rx";
1908 	bpmp: bpmp {  label
1909 		compatible = "nvidia,tegra186-bpmp";
1924 			compatible = "nvidia,tegra186-bpmp-i2c";
1925 			nvidia,bpmp-bus-id = <5>;
1932 			compatible = "nvidia,tegra186-bpmp-thermal";
2057 		clocks = <&bpmp TEGRA186_CLK_PLLA>,
2058 			 <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
2060 		assigned-clocks = <&bpmp TEGRA186_CLK_PLLA>,
2061 				  <&bpmp TEGRA186_CLK_PLL_A_OUT0>,
2062 				  <&bpmp TEGRA186_CLK_AUD_MCLK>;
2064 					 <&bpmp TEGRA186_CLK_PLLA>,
2065 					 <&bpmp TEGRA186_CLK_PLL_A_OUT0>;