dts/microchip/sparx5_pcb135_board.dtsi

1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
10 	gpio-restart {
11 		compatible = "gpio-restart";
16 	i2c0_imux: i2c-mux {
17 		compatible = "i2c-mux-pinctrl";
18 		#address-cells = <1>;
19 		#size-cells = <0>;
20 		i2c-parent = <&i2c0>;
24 		compatible = "gpio-leds";
25 		led-0 {
28 			default-state = "off";
30 		led-1 {
33 			default-state = "off";
35 		led-2 {
38 			default-state = "off";
40 		led-3 {
43 			default-state = "off";
45 		led-4 {
48 			default-state = "off";
50 		led-5 {
53 			default-state = "off";
55 		led-6 {
58 			default-state = "off";
60 		led-7 {
63 			default-state = "off";
67 	sfp_eth60: sfp-eth60 {
69 		i2c-bus = <&i2c_sfp1>;
70 		tx-disable-gpios = <&sgpio_out2 28 0 GPIO_ACTIVE_LOW>;
71 		rate-select0-gpios = <&sgpio_out2 28 1 GPIO_ACTIVE_HIGH>;
72 		los-gpios = <&sgpio_in2 28 0 GPIO_ACTIVE_HIGH>;
73 		mod-def0-gpios = <&sgpio_in2 28 1 GPIO_ACTIVE_LOW>;
74 		tx-fault-gpios = <&sgpio_in2 28 2 GPIO_ACTIVE_HIGH>;
77 	sfp_eth61: sfp-eth61 {
79 		i2c-bus = <&i2c_sfp2>;
80 		tx-disable-gpios = <&sgpio_out2 29 0 GPIO_ACTIVE_LOW>;
81 		rate-select0-gpios = <&sgpio_out2 29 1 GPIO_ACTIVE_HIGH>;
82 		los-gpios = <&sgpio_in2 29 0 GPIO_ACTIVE_HIGH>;
83 		mod-def0-gpios = <&sgpio_in2 29 1 GPIO_ACTIVE_LOW>;
84 		tx-fault-gpios = <&sgpio_in2 29 2 GPIO_ACTIVE_HIGH>;
87 	sfp_eth62: sfp-eth62 {
89 		i2c-bus = <&i2c_sfp3>;
90 		tx-disable-gpios = <&sgpio_out2 30 0 GPIO_ACTIVE_LOW>;
91 		rate-select0-gpios = <&sgpio_out2 30 1 GPIO_ACTIVE_HIGH>;
92 		los-gpios = <&sgpio_in2 30 0 GPIO_ACTIVE_HIGH>;
93 		mod-def0-gpios = <&sgpio_in2 30 1 GPIO_ACTIVE_LOW>;
94 		tx-fault-gpios = <&sgpio_in2 30 2 GPIO_ACTIVE_HIGH>;
97 	sfp_eth63: sfp-eth63 {
99 		i2c-bus = <&i2c_sfp4>;
100 		tx-disable-gpios = <&sgpio_out2 31 0 GPIO_ACTIVE_LOW>;
101 		rate-select0-gpios = <&sgpio_out2 31 1 GPIO_ACTIVE_HIGH>;
102 		los-gpios = <&sgpio_in2 31 0 GPIO_ACTIVE_HIGH>;
103 		mod-def0-gpios = <&sgpio_in2 31 1 GPIO_ACTIVE_LOW>;
104 		tx-fault-gpios = <&sgpio_in2 31 2 GPIO_ACTIVE_HIGH>;
109 	i2cmux_pins_i: i2cmux-pins {
113 		output-low;
115 	i2cmux_s29: i2cmux-0-pins {
118 		output-high;
120 	i2cmux_s30: i2cmux-1-pins {
123 		output-high;
125 	i2cmux_s31: i2cmux-2-pins {
128 		output-high;
130 	i2cmux_s32: i2cmux-3-pins {
133 		output-high;
140 		compatible = "spi-mux";
141 		mux-controls = <&mux>;
142 		#address-cells = <1>;
143 		#size-cells = <0>;
146 			compatible = "jedec,spi-nor";
147 			spi-max-frequency = <8000000>;
155 	microchip,sgpio-port-ranges = <24 31>;
166 	microchip,sgpio-port-ranges = <0 0>, <16 18>, <28 31>;
170 	pinctrl-names =
173 	pinctrl-0 = <&i2cmux_s29>;
174 	pinctrl-1 = <&i2cmux_s30>;
175 	pinctrl-2 = <&i2cmux_s31>;
176 	pinctrl-3 = <&i2cmux_s32>;
177 	pinctrl-4 = <&i2cmux_pins_i>;
180 		#address-cells = <1>;
181 		#size-cells = <0>;
185 		#address-cells = <1>;
186 		#size-cells = <0>;
190 		#address-cells = <1>;
191 		#size-cells = <0>;
195 		#address-cells = <1>;
196 		#size-cells = <0>;
202 	phy0: ethernet-phy@0 {
205 	phy1: ethernet-phy@1 {
208 	phy2: ethernet-phy@2 {
211 	phy3: ethernet-phy@3 {
214 	phy4: ethernet-phy@4 {
217 	phy5: ethernet-phy@5 {
220 	phy6: ethernet-phy@6 {
223 	phy7: ethernet-phy@7 {
226 	phy8: ethernet-phy@8 {
229 	phy9: ethernet-phy@9 {
232 	phy10: ethernet-phy@10 {
233 		reg = <10>;
235 	phy11: ethernet-phy@11 {
238 	phy12: ethernet-phy@12 {
241 	phy13: ethernet-phy@13 {
244 	phy14: ethernet-phy@14 {
247 	phy15: ethernet-phy@15 {
250 	phy16: ethernet-phy@16 {
253 	phy17: ethernet-phy@17 {
256 	phy18: ethernet-phy@18 {
259 	phy19: ethernet-phy@19 {
262 	phy20: ethernet-phy@20 {
265 	phy21: ethernet-phy@21 {
268 	phy22: ethernet-phy@22 {
271 	phy23: ethernet-phy@23 {
278 	phy24: ethernet-phy@24 {
281 	phy25: ethernet-phy@25 {
284 	phy26: ethernet-phy@26 {
287 	phy27: ethernet-phy@27 {
290 	phy28: ethernet-phy@28 {
293 	phy29: ethernet-phy@29 {
296 	phy30: ethernet-phy@30 {
299 	phy31: ethernet-phy@31 {
302 	phy32: ethernet-phy@32 {
305 	phy33: ethernet-phy@33 {
308 	phy34: ethernet-phy@34 {
309 		reg = <10>;
311 	phy35: ethernet-phy@35 {
314 	phy36: ethernet-phy@36 {
317 	phy37: ethernet-phy@37 {
320 	phy38: ethernet-phy@38 {
323 	phy39: ethernet-phy@39 {
326 	phy40: ethernet-phy@40 {
329 	phy41: ethernet-phy@41 {
332 	phy42: ethernet-phy@42 {
335 	phy43: ethernet-phy@43 {
338 	phy44: ethernet-phy@44 {
341 	phy45: ethernet-phy@45 {
344 	phy46: ethernet-phy@46 {
347 	phy47: ethernet-phy@47 {
354 	phy64: ethernet-phy@64 {
360 	ethernet-ports {
361 		#address-cells = <1>;
362 		#size-cells = <0>;
368 			phy-handle = <&phy0>;
369 			phy-mode = "qsgmii";
375 			phy-handle = <&phy1>;
376 			phy-mode = "qsgmii";
382 			phy-handle = <&phy2>;
383 			phy-mode = "qsgmii";
389 			phy-handle = <&phy3>;
390 			phy-mode = "qsgmii";
396 			phy-handle = <&phy4>;
397 			phy-mode = "qsgmii";
403 			phy-handle = <&phy5>;
404 			phy-mode = "qsgmii";
410 			phy-handle = <&phy6>;
411 			phy-mode = "qsgmii";
417 			phy-handle = <&phy7>;
418 			phy-mode = "qsgmii";
424 			phy-handle = <&phy8>;
425 			phy-mode = "qsgmii";
431 			phy-handle = <&phy9>;
432 			phy-mode = "qsgmii";
434 		port10: port@10 {
435 			reg = <10>;
438 			phy-handle = <&phy10>;
439 			phy-mode = "qsgmii";
445 			phy-handle = <&phy11>;
446 			phy-mode = "qsgmii";
452 			phy-handle = <&phy12>;
453 			phy-mode = "qsgmii";
459 			phy-handle = <&phy13>;
460 			phy-mode = "qsgmii";
466 			phy-handle = <&phy14>;
467 			phy-mode = "qsgmii";
473 			phy-handle = <&phy15>;
474 			phy-mode = "qsgmii";
480 			phy-handle = <&phy16>;
481 			phy-mode = "qsgmii";
487 			phy-handle = <&phy17>;
488 			phy-mode = "qsgmii";
494 			phy-handle = <&phy18>;
495 			phy-mode = "qsgmii";
501 			phy-handle = <&phy19>;
502 			phy-mode = "qsgmii";
508 			phy-handle = <&phy20>;
509 			phy-mode = "qsgmii";
515 			phy-handle = <&phy21>;
516 			phy-mode = "qsgmii";
522 			phy-handle = <&phy22>;
523 			phy-mode = "qsgmii";
529 			phy-handle = <&phy23>;
530 			phy-mode = "qsgmii";
536 			phy-handle = <&phy24>;
537 			phy-mode = "qsgmii";
543 			phy-handle = <&phy25>;
544 			phy-mode = "qsgmii";
550 			phy-handle = <&phy26>;
551 			phy-mode = "qsgmii";
557 			phy-handle = <&phy27>;
558 			phy-mode = "qsgmii";
564 			phy-handle = <&phy28>;
565 			phy-mode = "qsgmii";
571 			phy-handle = <&phy29>;
572 			phy-mode = "qsgmii";
578 			phy-handle = <&phy30>;
579 			phy-mode = "qsgmii";
585 			phy-handle = <&phy31>;
586 			phy-mode = "qsgmii";
592 			phy-handle = <&phy32>;
593 			phy-mode = "qsgmii";
599 			phy-handle = <&phy33>;
600 			phy-mode = "qsgmii";
606 			phy-handle = <&phy34>;
607 			phy-mode = "qsgmii";
613 			phy-handle = <&phy35>;
614 			phy-mode = "qsgmii";
620 			phy-handle = <&phy36>;
621 			phy-mode = "qsgmii";
627 			phy-handle = <&phy37>;
628 			phy-mode = "qsgmii";
634 			phy-handle = <&phy38>;
635 			phy-mode = "qsgmii";
641 			phy-handle = <&phy39>;
642 			phy-mode = "qsgmii";
648 			phy-handle = <&phy40>;
649 			phy-mode = "qsgmii";
655 			phy-handle = <&phy41>;
656 			phy-mode = "qsgmii";
662 			phy-handle = <&phy42>;
663 			phy-mode = "qsgmii";
669 			phy-handle = <&phy43>;
670 			phy-mode = "qsgmii";
676 			phy-handle = <&phy44>;
677 			phy-mode = "qsgmii";
683 			phy-handle = <&phy45>;
684 			phy-mode = "qsgmii";
690 			phy-handle = <&phy46>;
691 			phy-mode = "qsgmii";
697 			phy-handle = <&phy47>;
698 			phy-mode = "qsgmii";
705 			phy-mode = "10gbase-r";
707 			managed = "in-band-status";
713 			phy-mode = "10gbase-r";
715 			managed = "in-band-status";
721 			phy-mode = "10gbase-r";
723 			managed = "in-band-status";
729 			phy-mode = "10gbase-r";
731 			managed = "in-band-status";
738 			phy-handle = <&phy64>;
739 			phy-mode = "sgmii";