Lines Matching full:vppsys0
588 <&vppsys0 CLK_VPP0_SMI_COMMON>,
589 <&vppsys0 CLK_VPP0_GALS_VDO0_LARB0>,
590 <&vppsys0 CLK_VPP0_GALS_VDO0_LARB1>,
591 <&vppsys0 CLK_VPP0_GALS_VENCSYS>,
592 <&vppsys0 CLK_VPP0_GALS_VENCSYS_CORE1>,
593 <&vppsys0 CLK_VPP0_GALS_INFRA>,
594 <&vppsys0 CLK_VPP0_GALS_CAMSYS>,
595 <&vppsys0 CLK_VPP0_GALS_VPP1_LARB5>,
596 <&vppsys0 CLK_VPP0_GALS_VPP1_LARB6>,
597 <&vppsys0 CLK_VPP0_SMI_REORDER>,
598 <&vppsys0 CLK_VPP0_SMI_IOMMU>,
599 <&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>,
600 <&vppsys0 CLK_VPP0_GALS_EMI0_EMI1>,
601 <&vppsys0 CLK_VPP0_SMI_SUB_COMMON_REORDER>,
602 <&vppsys0 CLK_VPP0_SMI_RSI>,
603 <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>,
604 <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>,
605 <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>,
606 <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>;
609 "vppsys0-0", "vppsys0-1", "vppsys0-2", "vppsys0-3",
610 "vppsys0-4", "vppsys0-5", "vppsys0-6", "vppsys0-7",
611 "vppsys0-8", "vppsys0-9", "vppsys0-10", "vppsys0-11",
612 "vppsys0-12", "vppsys0-13", "vppsys0-14",
613 "vppsys0-15", "vppsys0-16", "vppsys0-17",
614 "vppsys0-18";
2027 vppsys0: syscon@14000000 { label
2028 compatible = "mediatek,mt8195-vppsys0", "syscon";
2043 clocks = <&vppsys0 CLK_VPP0_MDP_RDMA>;
2056 clocks = <&vppsys0 CLK_VPP0_MDP_FG>;
2063 clocks = <&vppsys0 CLK_VPP0_STITCH>;
2070 clocks = <&vppsys0 CLK_VPP0_MDP_HDR>;
2078 clocks = <&vppsys0 CLK_VPP0_MDP_AAL>;
2088 clocks = <&vppsys0 CLK_VPP0_MDP_RSZ>;
2095 clocks = <&vppsys0 CLK_VPP0_MDP_TDSHP>;
2103 clocks = <&vppsys0 CLK_VPP0_MDP_COLOR>;
2112 clocks = <&vppsys0 CLK_VPP0_MDP_OVL>;
2121 clocks = <&vppsys0 CLK_VPP0_PADDING>;
2129 clocks = <&vppsys0 CLK_VPP0_MDP_TCC>;
2138 clocks = <&vppsys0 CLK_VPP0_MDP_WROT>;
2149 clocks = <&vppsys0 CLK_VPP0_MUTEX>;
2156 clocks = <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>,
2157 <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>,
2158 <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>;
2167 clocks = <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>,
2168 <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>,
2169 <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>;
2178 clocks = <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>,
2179 <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>,
2180 <&vppsys0 CLK_VPP0_SMI_RSI>,
2181 <&vppsys0 CLK_VPP0_SMI_RSI>;
2191 clocks = <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>,
2192 <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>;
2205 clocks = <&vppsys0 CLK_VPP0_SMI_IOMMU>;
2247 <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>;
2275 <&vppsys0 CLK_VPP0_GALS_VPP1_LARB5>;
2287 <&vppsys0 CLK_VPP0_GALS_VPP1_LARB6>;
2598 <&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>;
2717 <&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>;
2924 clocks = <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>,
2958 clocks = <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>,
3135 <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>;
3279 <&vppsys0 CLK_VPP0_GALS_VDO0_LARB0>;
3290 <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>,
3291 <&vppsys0 CLK_VPP0_GALS_VDO0_LARB1>;
3362 <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>;