dts/mediatek/mt8195.dtsi

489 		infracfg_ao: syscon@10001000 {  label
490 			compatible = "mediatek,mt8195-infracfg_ao", "syscon", "simple-mfd";
546 						mediatek,infracfg = <&infracfg_ao>;
615 					mediatek,infracfg = <&infracfg_ao>;
624 						mediatek,infracfg = <&infracfg_ao>;
632 						mediatek,infracfg = <&infracfg_ao>;
648 						mediatek,infracfg = <&infracfg_ao>;
660 							mediatek,infracfg = <&infracfg_ao>;
672 							mediatek,infracfg = <&infracfg_ao>;
680 							mediatek,infracfg = <&infracfg_ao>;
688 							mediatek,infracfg = <&infracfg_ao>;
696 							mediatek,infracfg = <&infracfg_ao>;
708 							mediatek,infracfg = <&infracfg_ao>;
715 								mediatek,infracfg = <&infracfg_ao>;
721 								mediatek,infracfg = <&infracfg_ao>;
738 							mediatek,infracfg = <&infracfg_ao>;
754 								mediatek,infracfg = <&infracfg_ao>;
768 							mediatek,infracfg = <&infracfg_ao>;
793 					mediatek,infracfg = <&infracfg_ao>;
799 					mediatek,infracfg = <&infracfg_ao>;
835 					mediatek,infracfg = <&infracfg_ao>;
843 							 <&infracfg_ao CLK_INFRA_AO_AUDIO_26M_B>;
846 						mediatek,infracfg = <&infracfg_ao>;
879 			clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>,
880 				 <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>;
891 			clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>,
892 				 <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>,
917 			clocks = <&infracfg_ao CLK_INFRA_AO_GCE>;
925 			clocks = <&infracfg_ao CLK_INFRA_AO_GCE2>;
1006 				<&infracfg_ao CLK_INFRA_AO_AUDIO_26M_B>,
1035 			clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART0>;
1045 			clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART1>;
1055 			clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART2>;
1065 			clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART3>;
1075 			clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART4>;
1085 			clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART5>;
1094 			clocks = <&infracfg_ao CLK_INFRA_AO_AUXADC>;
1115 				 <&infracfg_ao CLK_INFRA_AO_SPI0>;
1124 			clocks = <&infracfg_ao CLK_INFRA_AO_THERM>;
1125 			resets = <&infracfg_ao MT8195_INFRA_RST0_THERM_CTRL_SWRST>;
1135 			clocks = <&infracfg_ao CLK_INFRA_AO_THERM>;
1139 			resets = <&infracfg_ao MT8195_INFRA_RST3_THERM_CTRL_PTP_SWRST>;
1150 				 <&infracfg_ao CLK_INFRA_AO_DISP_PWM>;
1161 				 <&infracfg_ao CLK_INFRA_AO_DISP_PWM1>;
1175 				 <&infracfg_ao CLK_INFRA_AO_SPI1>;
1189 				 <&infracfg_ao CLK_INFRA_AO_SPI2>;
1203 				 <&infracfg_ao CLK_INFRA_AO_SPI3>;
1217 				 <&infracfg_ao CLK_INFRA_AO_SPI4>;
1231 				 <&infracfg_ao CLK_INFRA_AO_SPI5>;
1240 			clocks = <&infracfg_ao CLK_INFRA_AO_SPIS0>;
1251 			clocks = <&infracfg_ao CLK_INFRA_AO_SPIS1>;
1282 			mediatek,pericfg = <&infracfg_ao>;
1358 			clocks = <&infracfg_ao CLK_INFRA_AO_SSUSB>,
1360 				 <&infracfg_ao CLK_INFRA_AO_SSUSB_XHCI>;
1376 				clocks = <&infracfg_ao CLK_INFRA_AO_SSUSB>,
1380 					 <&infracfg_ao CLK_INFRA_AO_SSUSB_XHCI>;
1393 				 <&infracfg_ao CLK_INFRA_AO_MSDC0>,
1394 				 <&infracfg_ao CLK_INFRA_AO_MSDC0_SRC>;
1406 				 <&infracfg_ao CLK_INFRA_AO_MSDC1>,
1407 				 <&infracfg_ao CLK_INFRA_AO_MSDC1_SRC>;
1421 				 <&infracfg_ao CLK_INFRA_AO_CG1_MSDC2>,
1422 				 <&infracfg_ao CLK_INFRA_AO_CG3_MSDC2>;
1433 			clocks = <&infracfg_ao CLK_INFRA_AO_THERM>;
1434 			resets = <&infracfg_ao MT8195_INFRA_RST4_THERM_CTRL_MCU_SWRST>;
1546 			clocks = <&infracfg_ao CLK_INFRA_AO_PCIE_PL_P_250M_P0>,
1547 				 <&infracfg_ao CLK_INFRA_AO_PCIE_TL_26M>,
1548 				 <&infracfg_ao CLK_INFRA_AO_PCIE_TL_96M>,
1549 				 <&infracfg_ao CLK_INFRA_AO_PCIE_TL_32K>,
1550 				 <&infracfg_ao CLK_INFRA_AO_PCIE_PERI_26M>,
1562 			resets = <&infracfg_ao MT8195_INFRA_RST2_PCIE_P0_SWRST>;
1598 			clocks = <&infracfg_ao CLK_INFRA_AO_PCIE_PL_P_250M_P1>,
1600 				 <&infracfg_ao CLK_INFRA_AO_PCIE_P1_TL_96M>,
1602 				 <&infracfg_ao CLK_INFRA_AO_PCIE_P1_PERI_26M>,
1614 			resets = <&infracfg_ao MT8195_INFRA_RST2_PCIE_P1_SWRST>;
1794 				 <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
1809 				 <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
1824 				 <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
1845 				 <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
1860 				 <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
1875 				 <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
1890 				 <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
1905 				 <&infracfg_ao CLK_INFRA_AO_APDMA_B>;