Lines Matching full:iommu0
1509 iommus = <&iommu0 M4U_PORT_L0_OVL_RDMA0>,
1510 <&iommu0 M4U_PORT_L0_OVL_RDMA0_HDR>;
1521 iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0>,
1522 <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0_HDR>;
1532 iommus = <&iommu0 M4U_PORT_L0_DISP_RDMA0>;
1621 iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2>,
1622 <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2_HDR>;
1633 iommus = <&iommu0 M4U_PORT_L1_DISP_RDMA4>;
1649 iommu0: m4u@1401d000 { label
1702 iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>;
1711 iommus = <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD_EXT>,
1712 <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD2_EXT>,
1713 <&iommu0 M4U_PORT_L5_VDEC_LAT0_AVC_MV_EXT>,
1714 <&iommu0 M4U_PORT_L5_VDEC_LAT0_PRED_RD_EXT>,
1715 <&iommu0 M4U_PORT_L5_VDEC_LAT0_TILE_EXT>,
1716 <&iommu0 M4U_PORT_L5_VDEC_LAT0_WDMA_EXT>,
1717 <&iommu0 M4U_PORT_L5_VDEC_LAT0_RG_CTRL_DMA_EXT>,
1718 <&iommu0 M4U_PORT_L5_VDEC_UFO_ENC_EXT>;
1734 iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>,
1735 <&iommu0 M4U_PORT_L4_VDEC_UFO_EXT>,
1736 <&iommu0 M4U_PORT_L4_VDEC_PP_EXT>,
1737 <&iommu0 M4U_PORT_L4_VDEC_PRED_RD_EXT>,
1738 <&iommu0 M4U_PORT_L4_VDEC_PRED_WR_EXT>,
1739 <&iommu0 M4U_PORT_L4_VDEC_PPWRAP_EXT>,
1740 <&iommu0 M4U_PORT_L4_VDEC_TILE_EXT>,
1741 <&iommu0 M4U_PORT_L4_VDEC_VLD_EXT>,
1742 <&iommu0 M4U_PORT_L4_VDEC_VLD2_EXT>,
1743 <&iommu0 M4U_PORT_L4_VDEC_AVC_MV_EXT>,
1744 <&iommu0 M4U_PORT_L4_VDEC_RG_CTRL_DMA_EXT>;
1811 iommus = <&iommu0 M4U_PORT_L7_VENC_RCPU>,
1812 <&iommu0 M4U_PORT_L7_VENC_REC>,
1813 <&iommu0 M4U_PORT_L7_VENC_BSDMA>,
1814 <&iommu0 M4U_PORT_L7_VENC_SV_COMV>,
1815 <&iommu0 M4U_PORT_L7_VENC_RD_COMV>,
1816 <&iommu0 M4U_PORT_L7_VENC_CUR_LUMA>,
1817 <&iommu0 M4U_PORT_L7_VENC_CUR_CHROMA>,
1818 <&iommu0 M4U_PORT_L7_VENC_REF_LUMA>,
1819 <&iommu0 M4U_PORT_L7_VENC_REF_CHROMA>,
1820 <&iommu0 M4U_PORT_L7_VENC_SUB_R_LUMA>,
1821 <&iommu0 M4U_PORT_L7_VENC_SUB_W_LUMA>;