dts/mediatek/mt8188.dtsi

910 		infracfg_ao: syscon@10001000 {  label
964 						mediatek,infracfg = <&infracfg_ao>;
1025 					mediatek,infracfg = <&infracfg_ao>;
1044 						mediatek,infracfg = <&infracfg_ao>;
1060 							mediatek,infracfg = <&infracfg_ao>;
1068 							mediatek,infracfg = <&infracfg_ao>;
1076 							mediatek,infracfg = <&infracfg_ao>;
1087 							mediatek,infracfg = <&infracfg_ao>;
1102 								mediatek,infracfg = <&infracfg_ao>;
1140 							mediatek,infracfg = <&infracfg_ao>;
1150 								mediatek,infracfg = <&infracfg_ao>;
1156 								mediatek,infracfg = <&infracfg_ao>;
1162 								mediatek,infracfg = <&infracfg_ao>;
1175 							mediatek,infracfg = <&infracfg_ao>;
1184 							mediatek,infracfg = <&infracfg_ao>;
1192 					mediatek,infracfg = <&infracfg_ao>;
1216 					mediatek,infracfg = <&infracfg_ao>;
1223 						mediatek,infracfg = <&infracfg_ao>;
1232 							mediatek,infracfg = <&infracfg_ao>;
1242 							mediatek,infracfg = <&infracfg_ao>;
1248 							mediatek,infracfg = <&infracfg_ao>;
1258 					mediatek,infracfg = <&infracfg_ao>;
1289 			clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>,
1290 				 <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>;
1299 			clocks = <&infracfg_ao CLK_INFRA_AO_GCE>;
1307 			clocks = <&infracfg_ao CLK_INFRA_AO_GCE2>;
1328 			clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART0>;
1337 			clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART1>;
1346 			clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART2>;
1355 			clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART3>;
1363 			clocks = <&infracfg_ao CLK_INFRA_AO_AUXADC>;
1383 				 <&infracfg_ao CLK_INFRA_AO_SPI0>;
1392 			clocks = <&infracfg_ao CLK_INFRA_AO_THERM>;
1393 			resets = <&infracfg_ao MT8188_INFRA_RST1_THERMAL_CTRL_RST>;
1407 				 <&infracfg_ao CLK_INFRA_AO_SPI1>;
1420 				 <&infracfg_ao CLK_INFRA_AO_SPI2>;
1433 				 <&infracfg_ao CLK_INFRA_AO_SPI3>;
1446 				 <&infracfg_ao CLK_INFRA_AO_SPI4>;
1459 				 <&infracfg_ao CLK_INFRA_AO_SPI5>;
1491 				 <&infracfg_ao CLK_INFRA_AO_MSDC0>,
1492 				 <&infracfg_ao CLK_INFRA_AO_MSDC0_SRC>,
1493 				 <&infracfg_ao CLK_INFRA_AO_RG_AES_MSDCFDE_CK_0P>;
1504 				 <&infracfg_ao CLK_INFRA_AO_MSDC1>,
1505 				 <&infracfg_ao CLK_INFRA_AO_MSDC1_SRC>;
1516 			clocks = <&infracfg_ao CLK_INFRA_AO_THERM>;
1517 			resets = <&infracfg_ao MT8188_INFRA_RST1_THERMAL_MCU_RST>;
1530 				 <&infracfg_ao CLK_INFRA_AO_APDMA_BCLK>;
1544 				 <&infracfg_ao CLK_INFRA_AO_APDMA_BCLK>;
1558 				 <&infracfg_ao CLK_INFRA_AO_APDMA_BCLK>;
1628 				 <&infracfg_ao CLK_INFRA_AO_APDMA_BCLK>;
1642 				 <&infracfg_ao CLK_INFRA_AO_APDMA_BCLK>;
1719 				 <&infracfg_ao CLK_INFRA_AO_APDMA_BCLK>;
1733 				 <&infracfg_ao CLK_INFRA_AO_APDMA_BCLK>;