dts/mediatek/mt7988a.dtsi

1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
3 #include <dt-bindings/clock/mediatek,mt7988-clk.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/phy/phy.h>
9 	interrupt-parent = <&gic>;
10 	#address-cells = <2>;
11 	#size-cells = <2>;
14 		#address-cells = <1>;
15 		#size-cells = <0>;
18 			compatible = "arm,cortex-a73";
21 			enable-method = "psci";
25 			compatible = "arm,cortex-a73";
28 			enable-method = "psci";
32 			compatible = "arm,cortex-a73";
35 			enable-method = "psci";
39 			compatible = "arm,cortex-a73";
42 			enable-method = "psci";
46 	oscillator-40m {
47 		compatible = "fixed-clock";
48 		clock-frequency = <40000000>;
49 		#clock-cells = <0>;
50 		clock-output-names = "clkxtal";
54 		compatible = "arm,cortex-a73-pmu";
55 		interrupt-parent = <&gic>;
60 		compatible = "arm,psci-0.2";
65 		compatible = "simple-bus";
67 		#address-cells = <2>;
68 		#size-cells = <2>;
70 		gic: interrupt-controller@c000000 {
71 			compatible = "arm,gic-v3";
77 			interrupt-parent = <&gic>;
79 			interrupt-controller;
80 			#interrupt-cells = <3>;
83 		infracfg: clock-controller@10001000 {
84 			compatible = "mediatek,mt7988-infracfg", "syscon";
86 			#clock-cells = <1>;
89 		clock-controller@1001b000 {
90 			compatible = "mediatek,mt7988-topckgen", "syscon";
92 			#clock-cells = <1>;
96 			compatible = "mediatek,mt7988-wdt";
99 			#reset-cells = <1>;
102 		clock-controller@1001e000 {
103 			compatible = "mediatek,mt7988-apmixedsys";
105 			#clock-cells = <1>;
109 			compatible = "mediatek,mt7988-pwm";
121 			clock-names = "top", "main", "pwm1", "pwm2", "pwm3",
123 			#pwm-cells = <2>;
128 			compatible = "mediatek,mt7981-i2c";
134 			clock-names = "main", "dma";
135 			#address-cells = <1>;
136 			#size-cells = <0>;
141 			compatible = "mediatek,mt7981-i2c";
147 			clock-names = "main", "dma";
148 			#address-cells = <1>;
149 			#size-cells = <0>;
154 			compatible = "mediatek,mt7981-i2c";
160 			clock-names = "main", "dma";
161 			#address-cells = <1>;
162 			#size-cells = <0>;
167 			compatible = "mediatek,mt7988-xhci", "mediatek,mtk-xhci";
170 			reg-names = "mac", "ippc";
177 			clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck";
181 			compatible = "mediatek,mt7988-xhci", "mediatek,mtk-xhci";
184 			reg-names = "mac", "ippc";
191 			clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck";
194 		clock-controller@11f40000 {
195 			compatible = "mediatek,mt7988-xfi-pll";
198 			#clock-cells = <1>;
201 		clock-controller@15000000 {
202 			compatible = "mediatek,mt7988-ethsys", "syscon";
204 			#clock-cells = <1>;
205 			#reset-cells = <1>;
208 		clock-controller@15031000 {
209 			compatible = "mediatek,mt7988-ethwarp";
211 			#clock-cells = <1>;
212 			#reset-cells = <1>;
217 		compatible = "arm,armv8-timer";
218 		interrupt-parent = <&gic>;