dts/mediatek/mt7622.dtsi

86 		cpu1: cpu@1 {
217 		#clock-cells = <1>;
218 		#reset-cells = <1>;
237 		#clock-cells = <1>;
238 		#reset-cells = <1>;
244 		#power-domain-cells = <1>;
278 		#address-cells = <1>;
279 		#size-cells = <1>;
289 		#clock-cells = <1>;
295 		#clock-cells = <1>;
348 		#address-cells = <1>;
349 		#size-cells = <1>;
387 		#io-channel-cells = <1>;
461 		#address-cells = <1>;
475 		#address-cells = <1>;
489 		#address-cells = <1>;
502 		#address-cells = <1>;
508 		#thermal-sensor-cells = <1>;
548 		#address-cells = <1>;
560 		#address-cells = <1>;
581 		#address-cells = <1>;
594 		#address-cells = <1>;
613 		#clock-cells = <1>;
734 	ssusbsys: clock-controller@1a000000 {
737 		#clock-cells = <1>;
738 		#reset-cells = <1>;
741 	ssusb: usb@1a0c0000 {
761 	u3phy: t-phy@1a0c4000 {
770 		u2port0: usb-phy@1a0c4800 {
772 			#phy-cells = <1>;
777 		u3port0: usb-phy@1a0c4900 {
779 			#phy-cells = <1>;
784 		u2port1: usb-phy@1a0c5000 {
786 			#phy-cells = <1>;
792 	pciesys: clock-controller@1a100800 {
795 		#clock-cells = <1>;
796 		#reset-cells = <1>;
799 	pciecfg: pciecfg@1a140000 {
804 	pcie0: pcie@1a143000 {
828 		#interrupt-cells = <1>;
830 		interrupt-map = <0 0 0 1 &pcie_intc0 0>,
831 				<0 0 0 2 &pcie_intc0 1>,
837 			#interrupt-cells = <1>;
841 	pcie1: pcie@1a145000 {
846 		linux,pci-domain = <1>;
866 		#interrupt-cells = <1>;
868 		interrupt-map = <0 0 0 1 &pcie_intc1 0>,
869 				<0 0 0 2 &pcie_intc1 1>,
875 			#interrupt-cells = <1>;
879 	sata: sata@1a200000 {
911 		sata_port: sata-phy@1a243000 {
915 			#phy-cells = <1>;
919 	hifsys: clock-controller@1af00000 {
922 		#clock-cells = <1>;
925 	ethsys: clock-controller@1b000000 {
929 		#clock-cells = <1>;
930 		#reset-cells = <1>;
933 	hsdma: dma-controller@1b007000 {
940 		#dma-cells = <1>;
964 	eth: ethernet@1b100000 {
993 		#address-cells = <1>;
998 	sgmiisys: sgmiisys@1b128000 {
1002 		#clock-cells = <1>;