dts/mediatek/mt6755.dtsi

1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 	interrupt-parent = <&sysirq>;
13 	#address-cells = <2>;
14 	#size-cells = <2>;
17 		compatible = "arm,psci-0.2";
22 		#address-cells = <1>;
23 		#size-cells = <0>;
25 		cpu0: cpu@0 {
26 			device_type = "cpu";
27 			compatible = "arm,cortex-a53";
28 			enable-method = "psci";
32 		cpu1: cpu@1 {
33 			device_type = "cpu";
34 			compatible = "arm,cortex-a53";
35 			enable-method = "psci";
39 		cpu2: cpu@2 {
40 			device_type = "cpu";
41 			compatible = "arm,cortex-a53";
42 			enable-method = "psci";
46 		cpu3: cpu@3 {
47 			device_type = "cpu";
48 			compatible = "arm,cortex-a53";
49 			enable-method = "psci";
53 		cpu4: cpu@100 {
54 			device_type = "cpu";
55 			compatible = "arm,cortex-a53";
56 			enable-method = "psci";
60 		cpu5: cpu@101 {
61 			device_type = "cpu";
62 			compatible = "arm,cortex-a53";
63 			enable-method = "psci";
67 		cpu6: cpu@102 {
68 			device_type = "cpu";
69 			compatible = "arm,cortex-a53";
70 			enable-method = "psci";
74 		cpu7: cpu@103 {
75 			device_type = "cpu";
76 			compatible = "arm,cortex-a53";
77 			enable-method = "psci";
83 		compatible = "fixed-clock";
84 		clock-frequency = <26000000>;
85 		#clock-cells = <0>;
89 		compatible = "arm,armv8-timer";
90 		interrupt-parent = <&gic>;
101 	sysirq: intpol-controller@10200620 {
102 		compatible = "mediatek,mt6755-sysirq",
103 			     "mediatek,mt6577-sysirq";
104 		interrupt-controller;
105 		#interrupt-cells = <3>;
106 		interrupt-parent = <&gic>;
110 	gic: interrupt-controller@10231000 {
111 		compatible = "arm,gic-400";
112 		#interrupt-cells = <3>;
113 		interrupt-parent = <&gic>;
114 		interrupt-controller;
122 		compatible = "mediatek,mt6755-uart",
123 			     "mediatek,mt6577-uart";
131 		compatible = "mediatek,mt6755-uart",
132 			     "mediatek,mt6577-uart";