Lines Matching +full:0 +full:xe2000000
15 #define CP11X_PCIEx_MEM_BASE(iface) (0xe2000000 + (iface * 0x1000000))
16 #define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
37 #define CP11X_PCIEx_MEM_BASE(iface) (0xe5000000 + (iface * 0x1000000))
38 #define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
80 cooling-levels = <0 51 102 153 204 255>;
83 pinctrl-0 = <&cp0_fan_pwm_pins &cp0_fan_tacho_pins>;
101 pinctrl-0 = <&cp0_reg_ap_vhv_pins>;
112 pinctrl-0 = <&cp0_reg_cp_vhv_pins>;
137 pinctrl-0 = <&ap_mmc0_pins>;
173 pinctrl-0 = <&cp0_eth1_pins>;
201 pinctrl-0 = <&cp0_i2c0_pins>;
207 reg = <0x50>;
213 reg = <0x53>;
219 pinctrl-0 = <&cp0_i2c1_pins>;
225 reg = <0x77>;
228 #size-cells = <0>;
230 com_clkgen_i2c: i2c@0 {
232 #size-cells = <0>;
233 reg = <0>;
240 #size-cells = <0>;
248 #size-cells = <0>;
256 #size-cells = <0>;
264 #size-cells = <0>;
274 pinctrl-0 = <&cp0_mdio_pins>;
277 cp0_eth_phy0: ethernet-phy@0 {
278 reg = <0>;
284 pinctrl-0 = <&cp0_spi1_pins>;
287 flash@0 {
289 reg = <0>;
438 pinctrl-0 = <&cp1_spi1_pins>;
441 tpm@0 {
442 reg = <0>;
446 pinctrl-0 = <&cp1_tpm_irq_pins>;
697 phys = <&cp2_utmi0>, <&cp2_comphy1 0>;
709 pinctrl-0 = <&uart0_pins>;